From: Aleksandar Rikalo <arikalo@gmail.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Aleksandar Rikalo <arikalo@gmail.com>,
Chao-ying Fu <cfu@wavecomp.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Geert Uytterhoeven <geert@linux-m68k.org>,
Greg Ungerer <gerg@kernel.org>, Hauke Mehrtens <hauke@hauke-m.de>,
Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org,
Marc Zyngier <maz@kernel.org>,
Paul Burton <paulburton@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Serge Semin <fancer.lancer@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
Tiezhu Yang <yangtiezhu@loongson.cn>,
Gregory CLEMENT <gregory.clement@bootlin.com>
Subject: [PATCH v7 01/12] irqchip/mips-gic: Introduce for_each_online_cpu_gic()
Date: Sat, 19 Oct 2024 09:10:26 +0200 [thread overview]
Message-ID: <20241019071037.145314-2-arikalo@gmail.com> (raw)
In-Reply-To: <20241019071037.145314-1-arikalo@gmail.com>
From: Paul Burton <paulburton@kernel.org>
Parts of code in the MIPS GIC driver operate on the GIC local register
block for each online CPU, accessing each via the GIC's other/redirect
register block.
Abstract the process of iterating over online CPUs & configuring the
other/redirect region to access their registers through a new
for_each_online_cpu_gic() macro.
Signed-off-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: Chao-ying Fu <cfu@wavecomp.com>
Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com>
Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
Tested-by: Serge Semin <fancer.lancer@gmail.com>
---
drivers/irqchip/irq-mips-gic.c | 59 +++++++++++++++++++++++-----------
1 file changed, 41 insertions(+), 18 deletions(-)
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 76253e864f23..6c7a7d2f0438 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -66,6 +66,44 @@ static struct gic_all_vpes_chip_data {
bool mask;
} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
+static int __gic_with_next_online_cpu(int prev)
+{
+ unsigned int cpu;
+
+ /* Discover the next online CPU */
+ cpu = cpumask_next(prev, cpu_online_mask);
+
+ /* If there isn't one, we're done */
+ if (cpu >= nr_cpu_ids)
+ return cpu;
+
+ /*
+ * Move the access lock to the next CPU's GIC local register block.
+ *
+ * Set GIC_VL_OTHER. Since the caller holds gic_lock nothing can
+ * clobber the written value.
+ */
+ write_gic_vl_other(mips_cm_vp_id(cpu));
+
+ return cpu;
+}
+
+/**
+ * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
+ * @cpu: An integer variable to hold the current CPU number
+ * @gic_lock: A pointer to raw spin lock used as a guard
+ *
+ * Iterate over online CPUs & configure the other/redirect register region to
+ * access each CPUs GIC local register block, which can be accessed from the
+ * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or
+ * their derivatives.
+ */
+#define for_each_online_cpu_gic(cpu, gic_lock) \
+ guard(raw_spinlock_irqsave)(gic_lock); \
+ for ((cpu) = __gic_with_next_online_cpu(-1); \
+ (cpu) < nr_cpu_ids; \
+ (cpu) = __gic_with_next_online_cpu(cpu))
+
static void gic_clear_pcpu_masks(unsigned int intr)
{
unsigned int i;
@@ -350,37 +388,27 @@ static struct irq_chip gic_local_irq_controller = {
static void gic_mask_local_irq_all_vpes(struct irq_data *d)
{
struct gic_all_vpes_chip_data *cd;
- unsigned long flags;
int intr, cpu;
intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
cd = irq_data_get_irq_chip_data(d);
cd->mask = false;
- raw_spin_lock_irqsave(&gic_lock, flags);
- for_each_online_cpu(cpu) {
- write_gic_vl_other(mips_cm_vp_id(cpu));
+ for_each_online_cpu_gic(cpu, &gic_lock)
write_gic_vo_rmask(BIT(intr));
- }
- raw_spin_unlock_irqrestore(&gic_lock, flags);
}
static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
{
struct gic_all_vpes_chip_data *cd;
- unsigned long flags;
int intr, cpu;
intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
cd = irq_data_get_irq_chip_data(d);
cd->mask = true;
- raw_spin_lock_irqsave(&gic_lock, flags);
- for_each_online_cpu(cpu) {
- write_gic_vl_other(mips_cm_vp_id(cpu));
+ for_each_online_cpu_gic(cpu, &gic_lock)
write_gic_vo_smask(BIT(intr));
- }
- raw_spin_unlock_irqrestore(&gic_lock, flags);
}
static void gic_all_vpes_irq_cpu_online(void)
@@ -469,7 +497,6 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hwirq)
{
struct gic_all_vpes_chip_data *cd;
- unsigned long flags;
unsigned int intr;
int err, cpu;
u32 map;
@@ -533,12 +560,8 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
if (!gic_local_irq_is_routable(intr))
return -EPERM;
- raw_spin_lock_irqsave(&gic_lock, flags);
- for_each_online_cpu(cpu) {
- write_gic_vl_other(mips_cm_vp_id(cpu));
+ for_each_online_cpu_gic(cpu, &gic_lock)
write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
- }
- raw_spin_unlock_irqrestore(&gic_lock, flags);
return 0;
}
--
2.25.1
next prev parent reply other threads:[~2024-10-19 7:10 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-19 7:10 [PATCH v7 00/12] MIPS: Support I6500 multi-cluster configuration Aleksandar Rikalo
2024-10-19 7:10 ` Aleksandar Rikalo [this message]
2024-10-19 7:10 ` [PATCH v7 02/12] irqchip/mips-gic: Support multi-cluster in for_each_online_cpu_gic() Aleksandar Rikalo
2024-10-25 22:17 ` Thomas Gleixner
2024-10-19 7:10 ` [PATCH v7 03/12] irqchip/mips-gic: Setup defaults in each cluster Aleksandar Rikalo
2024-10-19 7:10 ` [PATCH v7 04/12] irqchip/mips-gic: Multi-cluster support Aleksandar Rikalo
2024-10-19 7:10 ` [PATCH v7 05/12] clocksource: mips-gic-timer: Always use cluster 0 counter as clocksource Aleksandar Rikalo
2024-10-28 14:54 ` Daniel Lezcano
2024-10-28 15:15 ` Thomas Bogendoerfer
2024-10-28 15:22 ` Daniel Lezcano
2024-10-28 15:47 ` Thomas Bogendoerfer
2024-10-28 16:09 ` Daniel Lezcano
2024-11-13 20:20 ` [tip: timers/core] clocksource/drivers/mips-gic-timer: " tip-bot2 for Paul Burton
2024-10-19 7:10 ` [PATCH v7 06/12] clocksource: mips-gic-timer: Enable counter when CPUs start Aleksandar Rikalo
2024-10-19 7:10 ` [PATCH v7 07/12] MIPS: pm-cps: Use per-CPU variables as per-CPU, not per-core Aleksandar Rikalo
2024-10-19 7:10 ` [PATCH v7 08/12] MIPS: CPS: Introduce struct cluster_boot_config Aleksandar Rikalo
2024-10-19 7:10 ` [PATCH v7 09/12] MIPS: CPS: Boot CPUs in secondary clusters Aleksandar Rikalo
2024-10-19 7:10 ` [PATCH v7 10/12] dt-bindings: mips: cpu: Add property for broken HCI information Aleksandar Rikalo
2024-10-21 6:10 ` Krzysztof Kozlowski
2024-10-19 7:10 ` [PATCH v7 11/12] MIPS: CPS: Support broken HCI for multicluster Aleksandar Rikalo
2024-10-19 7:10 ` [PATCH v7 12/12] MIPS: mobileye: dts: eyeq6h: Enable cluster support Aleksandar Rikalo
2024-10-25 15:07 ` [PATCH v7 00/12] MIPS: Support I6500 multi-cluster configuration Gregory CLEMENT
2024-10-25 15:58 ` Gregory CLEMENT
[not found] ` <CAGQJe6pywUi8dnhxFopkMfP2U1PceHjTPX-CysT0bajSk_AKKg@mail.gmail.com>
2024-10-28 13:39 ` Gregory CLEMENT
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