From: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
Andi Shyti <andi.shyti@kernel.org>,
Mark Brown <broonie@kernel.org>,
Alim Akhtar <alim.akhtar@samsung.com>,
Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v1 3/6] arm64: dts: exynos: Add clock management unit nodes
Date: Sun, 20 Oct 2024 21:21:18 +0300 [thread overview]
Message-ID: <20241020182121.377969-4-ivo.ivanov.ivanov1@gmail.com> (raw)
In-Reply-To: <20241020182121.377969-1-ivo.ivanov.ivanov1@gmail.com>
Add clock management unit nodes for:
- cmu_top, which provides muxes, divs and gates for other CMUs
- cmu_peris, which provides clocks for GIC and MCT
- cmu_fsys0, which provides clocks for USBDRD30
- cmu_fsys1, which provides clocks for MMC, UFS and PCIE
- cmu_peric0, which provides clocks for UART_DBG, USI00 ~ USI03
- cmu_peric1, which provides clocks for SPI_CAM0/1, UART_BT,
USI04 ~ USI13
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
---
arch/arm64/boot/dts/exynos/exynos8895.dtsi | 87 ++++++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi
index 223ebd482..802e135c4 100644
--- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi
@@ -5,6 +5,7 @@
* Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
*/
+#include <dt-bindings/clock/samsung,exynos8895.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -159,6 +160,15 @@ chipid@10000000 {
reg = <0x10000000 0x24>;
};
+ cmu_peris: clock-controller@10010000 {
+ compatible = "samsung,exynos8895-cmu-peris";
+ reg = <0x10010000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
+ clock-names = "oscclk", "bus";
+ };
+
gic: interrupt-controller@10201000 {
compatible = "arm,gic-400";
reg = <0x10201000 0x1000>,
@@ -173,24 +183,93 @@ gic: interrupt-controller@10201000 {
#size-cells = <1>;
};
+ cmu_peric0: clock-controller@10400000 {
+ compatible = "samsung,exynos8895-cmu-peric0";
+ reg = <0x10400000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>;
+ clock-names = "oscclk", "bus", "uart_dbg", "usi00",
+ "usi01", "usi02", "usi03";
+ };
+
pinctrl_peric0: pinctrl@104d0000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x104d0000 0x1000>;
interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
};
+ cmu_peric1: clock-controller@10800000 {
+ compatible = "samsung,exynos8895-cmu-peric1";
+ reg = <0x10800000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI04>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI05>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI06>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI07>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI08>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI09>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI10>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI11>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI12>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_USI13>;
+ clock-names = "oscclk", "bus", "speedy2", "cam0",
+ "cam1", "uart_bt", "usi04", "usi05",
+ "usi06", "usi07", "usi08", "usi09",
+ "usi10", "usi11", "usi12", "usi13";
+ };
+
pinctrl_peric1: pinctrl@10980000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x10980000 0x1000>;
interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
};
+ cmu_fsys0: clock-controller@11000000 {
+ compatible = "samsung,exynos8895-cmu-fsys0";
+ reg = <0x11000000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_FSYS0_BUS>,
+ <&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>,
+ <&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>;
+ clock-names = "oscclk", "bus",
+ "dpgtc", "mmc_embd",
+ "ufs_embd", "usbdrd30";
+ };
+
pinctrl_fsys0: pinctrl@11050000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x11050000 0x1000>;
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
};
+ cmu_fsys1: clock-controller@11400000 {
+ compatible = "samsung,exynos8895-cmu-fsys1";
+ reg = <0x11400000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
+ <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>,
+ <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
+ <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>;
+ clock-names = "oscclk", "bus", "mmc_card",
+ "pcie", "ufs_card";
+ };
+
pinctrl_fsys1: pinctrl@11430000 {
compatible = "samsung,exynos8895-pinctrl";
reg = <0x11430000 0x1000>;
@@ -213,6 +292,14 @@ pinctrl_busc: pinctrl@15a30000 {
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
};
+ cmu_top: clock-controller@15a80000 {
+ compatible = "samsung,exynos8895-cmu-top";
+ reg = <0x15a80000 0x8000>;
+ #clock-cells = <1>;
+ clocks = <&oscclk>;
+ clock-names = "oscclk";
+ };
+
pmu_system_controller: system-controller@16480000 {
compatible = "samsung,exynos8895-pmu",
"samsung,exynos7-pmu", "syscon";
--
2.43.0
next prev parent reply other threads:[~2024-10-20 18:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-20 18:21 [PATCH v1 0/6] arm64: dts: exynos8895: Add cmu, mct, serial_0/1 and spi_0/1 Ivaylo Ivanov
2024-10-20 18:21 ` [PATCH v1 1/6] dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible Ivaylo Ivanov
2024-10-21 9:45 ` Krzysztof Kozlowski
2024-10-20 18:21 ` [PATCH v1 2/6] spi: dt-bindings: samsung: Add a compatible for samsung,exynos8895-spi Ivaylo Ivanov
2024-10-21 9:46 ` Krzysztof Kozlowski
2024-10-20 18:21 ` Ivaylo Ivanov [this message]
2024-10-20 18:21 ` [PATCH v1 4/6] arm64: dts: exynos8895: Add Multi Core Timer (MCT) node Ivaylo Ivanov
2024-10-20 18:21 ` [PATCH v1 5/6] arm64: dts: exynos8895: Add serial_0/1 nodes Ivaylo Ivanov
2024-10-20 18:21 ` [PATCH v1 6/6] arm64: dts: exynos8895: Add spi_0/1 nodes Ivaylo Ivanov
2024-10-21 21:50 ` (subset) [PATCH v1 0/6] arm64: dts: exynos8895: Add cmu, mct, serial_0/1 and spi_0/1 Mark Brown
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