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AJvYcCW9xbNbd7kKcIwJkmfXwVGCLtJEsSkkJF3H7SCljl5YLbyqU0iSgpSazU6Uvg6OJROuHktjr9rKZ9SkgHI=@vger.kernel.org X-Gm-Message-State: AOJu0YxH2SvsixRpyTzqhlq0ClBAzscEcw89WgHxy/FgE1e4CfOgZCRe MIPS6aDre54G1U5ZnFQGiQJEJS/BBlIY8M5qIK4kmZc3KsBmGtLQQ03NNEgfVg== X-Google-Smtp-Source: AGHT+IHTS9yyMdGSpDBkN1ZywG4L881bK6lpw9juFK/sdg8K6E7YS49sKlIWRIuG+HaxSkMO8HbgaA== X-Received: by 2002:aa7:88d4:0:b0:71e:b8:1930 with SMTP id d2e1a72fcca58-71ea321e7famr21475298b3a.16.1729615569937; Tue, 22 Oct 2024 09:46:09 -0700 (PDT) Received: from thinkpad ([36.255.17.224]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-71ec13336d1sm4966249b3a.56.2024.10.22.09.46.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Oct 2024 09:46:09 -0700 (PDT) Date: Tue, 22 Oct 2024 22:16:03 +0530 From: Manivannan Sadhasivam To: Richard Zhu Cc: kw@linux.com, bhelgaas@google.com, lpieralisi@kernel.org, frank.li@nxp.com, l.stach@pengutronix.de, robh+dt@kernel.org, conor+dt@kernel.org, shawnguo@kernel.org, krzysztof.kozlowski+dt@linaro.org, festevam@gmail.com, s.hauer@pengutronix.de, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, imx@lists.linux.dev Subject: Re: [PATCH v4 2/9] PCI: imx6: Add ref clock for i.MX95 PCIe Message-ID: <20241022164603.gndz4vgbm2sgwtfj@thinkpad> References: <1728981213-8771-1-git-send-email-hongxing.zhu@nxp.com> <1728981213-8771-3-git-send-email-hongxing.zhu@nxp.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1728981213-8771-3-git-send-email-hongxing.zhu@nxp.com> On Tue, Oct 15, 2024 at 04:33:26PM +0800, Richard Zhu wrote: > Add "ref" clock to enable reference clock. > > If use external clock, ref clock should point to external reference. > > If use internal clock, CREF_EN in LAST_TO_REG controls reference output, > which implement in drivers/clk/imx/clk-imx95-blk-ctl.c. > So this means the driver won't work with old devicetrees. Am I right? Then you are breaking the DT compatibility. You should make the clock optional in the driver. - Mani > Signed-off-by: Richard Zhu > Reviewed-by: Frank Li > --- > drivers/pci/controller/dwc/pci-imx6.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 808d1f105417..52a8b2dc828a 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1480,6 +1480,7 @@ static const char * const imx8mm_clks[] = {"pcie_bus", "pcie", "pcie_aux"}; > static const char * const imx8mq_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux"}; > static const char * const imx6sx_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_inbound_axi"}; > static const char * const imx8q_clks[] = {"mstr", "slv", "dbi"}; > +static const char * const imx95_clks[] = {"pcie_bus", "pcie", "pcie_phy", "pcie_aux", "ref"}; > > static const struct imx_pcie_drvdata drvdata[] = { > [IMX6Q] = { > @@ -1593,8 +1594,8 @@ static const struct imx_pcie_drvdata drvdata[] = { > [IMX95] = { > .variant = IMX95, > .flags = IMX_PCIE_FLAG_HAS_SERDES, > - .clk_names = imx8mq_clks, > - .clks_cnt = ARRAY_SIZE(imx8mq_clks), > + .clk_names = imx95_clks, > + .clks_cnt = ARRAY_SIZE(imx95_clks), > .ltssm_off = IMX95_PE0_GEN_CTRL_3, > .ltssm_mask = IMX95_PCIE_LTSSM_EN, > .mode_off[0] = IMX95_PE0_GEN_CTRL_1, > -- > 2.37.1 > -- மணிவண்ணன் சதாசிவம்