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([77.85.230.22]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9a913704easm449177466b.107.2024.10.23.02.17.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Oct 2024 02:18:00 -0700 (PDT) From: Ivaylo Ivanov To: Krzysztof Kozlowski , Andi Shyti , Mark Brown , Alim Akhtar , Rob Herring , Conor Dooley , Daniel Lezcano , Thomas Gleixner Cc: linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/5] arm64: dts: exynos8895: Add cmu, mct, serial_0/1 and spi_0/1 Date: Wed, 23 Oct 2024 12:17:29 +0300 Message-ID: <20241023091734.538682-1-ivo.ivanov.ivanov1@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hey folks, This patchset adds device tree nodes for multiple clock management unit blocks, MCT, SPI and UART for Exynos8895. Exynos8895 uses USIv1 for most of its serial buses, except a few that have been implemented in this series. Support for USIv1 and HSI2C will be added in the future. This patchset is dependent on [1] and [2], which add driver support for CMU and UART. [1] https://lore.kernel.org/all/20241023090136.537395-1-ivo.ivanov.ivanov1@gmail.com/ [2] https://lore.kernel.org/all/20241023090902.538040-1-ivo.ivanov.ivanov1@gmail.com/ Changes in v2: - Add r-b from Krzysztof Kozlowski - Change clock-names according to the v2 changes for clk bindings Ivaylo Ivanov (5): dt-bindings: timer: exynos4210-mct: Add samsung,exynos8895-mct compatible arm64: dts: exynos8895: Add clock management unit nodes arm64: dts: exynos8895: Add Multi Core Timer (MCT) node arm64: dts: exynos8895: Add serial_0/1 nodes arm64: dts: exynos8895: Add spi_0/1 nodes .../timer/samsung,exynos4210-mct.yaml | 2 + arch/arm64/boot/dts/exynos/exynos8895.dtsi | 161 ++++++++++++++++++ 2 files changed, 163 insertions(+) -- 2.43.0