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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF00021F6A.mail.protection.outlook.com (10.167.249.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8093.14 via Frontend Transport; Fri, 25 Oct 2024 11:14:11 +0000 Received: from shatadru.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 25 Oct 2024 06:14:05 -0500 From: Dhananjay Ugwekar To: , , , , , , , , , , , , , CC: , , , , , , , "Dhananjay Ugwekar" Subject: [PATCH v6 00/10] Add RAPL core energy counter support for AMD CPUs Date: Fri, 25 Oct 2024 11:13:38 +0000 Message-ID: <20241025111348.3810-1-Dhananjay.Ugwekar@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6A:EE_|MW4PR12MB7216:EE_ X-MS-Office365-Filtering-Correlation-Id: e5ed5e8c-839b-43cd-1d66-08dcf4e62760 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|82310400026|376014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2024 11:14:11.9408 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e5ed5e8c-839b-43cd-1d66-08dcf4e62760 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7216 Currently the energy-cores event in the power PMU aggregates energy consumption data at a package level. On the other hand the core energy RAPL counter in AMD CPUs has a core scope (which means the energy consumption is recorded separately for each core). Earlier efforts to add the core event in the power PMU had failed [1], due to the difference in the scope of these two events. Hence, there is a need for a new core scope PMU. This patchset adds a new "power_core" PMU alongside the existing "power" PMU, which will be responsible for collecting the new "energy-core" event. Tested the package level and core level PMU counters with workloads pinned to different CPUs. Results with workload pinned to CPU 4 in core 4 on an AMD Zen4 Genoa machine: $ sudo perf stat --per-core -e power_core/energy-core/ -- taskset -c 4 stress-ng --matrix 1 --timeout 5s stress-ng: info: [21250] setting to a 5 second run per stressor stress-ng: info: [21250] dispatching hogs: 1 matrix stress-ng: info: [21250] successful run completed in 5.00s Performance counter stats for 'system wide': S0-D0-C0 1 0.00 Joules power_core/energy-core/ S0-D0-C1 1 0.00 Joules power_core/energy-core/ S0-D0-C2 1 0.00 Joules power_core/energy-core/ S0-D0-C3 1 0.00 Joules power_core/energy-core/ S0-D0-C4 1 8.43 Joules power_core/energy-core/ S0-D0-C5 1 0.00 Joules power_core/energy-core/ S0-D0-C6 1 0.00 Joules power_core/energy-core/ S0-D0-C7 1 0.00 Joules power_core/energy-core/ S0-D1-C8 1 0.00 Joules power_core/energy-core/ S0-D1-C9 1 0.00 Joules power_core/energy-core/ S0-D1-C10 1 0.00 Joules power_core/energy-core/ v5 Link: https://lore.kernel.org/all/20240913152149.6317-1-Dhananjay.Ugwekar@amd.com/ v6 Changes: * Rebase on top of V2 of Kan Liang's "PMU scope" patchset [2] * Modify the PMU name from "power_per_core" to "power_core" and event name from "event_per_core" to "event_core" Base: tip/master + [2] [1]: https://lore.kernel.org/lkml/3e766f0e-37d4-0f82-3868-31b14228868d@linux.intel.com/ [2]: https://lore.kernel.org/all/20241010142604.770192-1-kan.liang@linux.intel.com/ Dhananjay Ugwekar (9): perf/x86/rapl: Remove the unused get_rapl_pmu_cpumask() function perf/x86/rapl: Remove the cpu_to_rapl_pmu() function perf/x86/rapl: Rename rapl_pmu variables perf/x86/rapl: Make rapl_model struct global perf/x86/rapl: Add arguments to the init and cleanup functions perf/x86/rapl: Modify the generic variable names to *_pkg* perf/x86/rapl: Remove the global variable rapl_msrs perf/x86/rapl: Move the cntr_mask to rapl_pmus struct perf/x86/rapl: Add core energy counter support for AMD CPUs K Prateek Nayak (1): x86/topology: Introduce topology_logical_core_id() Documentation/arch/x86/topology.rst | 4 + arch/x86/events/rapl.c | 412 ++++++++++++++++---------- arch/x86/include/asm/processor.h | 1 + arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_common.c | 1 + 6 files changed, 268 insertions(+), 152 deletions(-) -- 2.34.1