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From: Lijuan Gao <quic_lijuang@quicinc.com>
To: Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>
Cc: <kernel@quicinc.com>, <linux-arm-msm@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	lijuang <quic_lijuang@quicinc.com>
Subject: [PATCH v5 5/5] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615
Date: Mon, 4 Nov 2024 17:10:12 +0800	[thread overview]
Message-ID: <20241104-add_initial_support_for_qcs615-v5-5-9dde8d7b80b0@quicinc.com> (raw)
In-Reply-To: <20241104-add_initial_support_for_qcs615-v5-0-9dde8d7b80b0@quicinc.com>

Enable clock controller, interconnect and pinctrl for Qualcomm QCS615
platform to boot to UART console.

The serial engine depends on GCC, interconnect, and pinctrl. It is
necessary to build them as built-in modules because the debug console
must be registered before userspace is launched. The primary reason for
this is that, for example, systemd opens /dev/console at launch (i.e.,
when the init process starts). Therefore, if we register the console after
this, we will not receive console output from systemd.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
---
 arch/arm64/configs/defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 0fad83642034..4657540d0c65 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -607,6 +607,7 @@ CONFIG_PINCTRL_MSM8996=y
 CONFIG_PINCTRL_MSM8998=y
 CONFIG_PINCTRL_QCM2290=y
 CONFIG_PINCTRL_QCS404=y
+CONFIG_PINCTRL_QCS615=y
 CONFIG_PINCTRL_QDF2XXX=y
 CONFIG_PINCTRL_QDU1000=y
 CONFIG_PINCTRL_SA8775P=y
@@ -1324,6 +1325,7 @@ CONFIG_MSM_MMCC_8998=m
 CONFIG_QCM_GCC_2290=y
 CONFIG_QCM_DISPCC_2290=m
 CONFIG_QCS_GCC_404=y
+CONFIG_QCS_GCC_615=y
 CONFIG_SC_CAMCC_7280=m
 CONFIG_QDU_GCC_1000=y
 CONFIG_SC_CAMCC_8280XP=m
@@ -1630,6 +1632,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y
 CONFIG_INTERCONNECT_QCOM_OSM_L3=m
 CONFIG_INTERCONNECT_QCOM_QCM2290=y
 CONFIG_INTERCONNECT_QCOM_QCS404=m
+CONFIG_INTERCONNECT_QCOM_QCS615=y
 CONFIG_INTERCONNECT_QCOM_QDU1000=y
 CONFIG_INTERCONNECT_QCOM_SA8775P=y
 CONFIG_INTERCONNECT_QCOM_SC7180=y

-- 
2.46.0


  parent reply	other threads:[~2024-11-04  9:10 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-04  9:10 [PATCH v5 0/5] Add initial support for QCS615 SoC and QCS615 RIDE board Lijuan Gao
2024-11-04  9:10 ` [PATCH v5 1/5] dt-bindings: arm: qcom: document QCS615 and the reference board Lijuan Gao
2024-11-04  9:10 ` [PATCH v5 2/5] dt-bindings: qcom,pdc: document QCS615 Power Domain Controller Lijuan Gao
2025-01-06 19:10   ` Rob Herring
2024-11-04  9:10 ` [PATCH v5 3/5] arm64: dts: qcom: add QCS615 platform Lijuan Gao
2024-11-04  9:10 ` [PATCH v5 4/5] arm64: dts: qcom: add base QCS615 RIDE Lijuan Gao
2024-11-04 11:12   ` Dmitry Baryshkov
2024-11-04  9:10 ` Lijuan Gao [this message]
2024-11-04 11:11   ` [PATCH v5 5/5] arm64: defconfig: enable clock controller, interconnect and pinctrl for QCS615 Dmitry Baryshkov
2024-12-02 15:51 ` (subset) [PATCH v5 0/5] Add initial support for QCS615 SoC and QCS615 RIDE board Bjorn Andersson

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