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Mon, 11 Nov 2024 23:13:54 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 11 Nov 2024 23:13:53 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Mon, 11 Nov 2024 23:13:53 -0800 Received: from localhost.localdomain (unknown [10.111.135.16]) by maili.marvell.com (Postfix) with ESMTP id 0A18F3F70B2; Mon, 11 Nov 2024 23:13:53 -0800 (PST) From: Jenishkumar Maheshbhai Patel To: , , , , , , , , CC: , , Jenishkumar Maheshbhai Patel Subject: [PATCH 1/1] arm64: dts: marvell: use reset controller to reset mac Date: Mon, 11 Nov 2024 23:13:50 -0800 Message-ID: <20241112071350.762111-1-jpatel2@marvell.com> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 3ZGkxgAhdUC6TpdclIJI6IyS3PWbiEOt X-Proofpoint-ORIG-GUID: 3ZGkxgAhdUC6TpdclIJI6IyS3PWbiEOt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.687,Hydra:6.0.235,FMLib:17.0.607.475 definitions=2020-10-13_15,2020-10-13_02,2020-04-07_01 change mac reset and mac reset bits to reset controller Signed-off-by: Jenishkumar Maheshbhai Patel --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index f5aef6a23f65..f358f9809edd 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -6,7 +6,7 @@ */ #include -#define CP11X_PCIEx_MAC_RESET_BIT_MASK(n) (0x1 << 11 + ((n + 2) % 3)) +#define CP11X_PCIEx_MAC_RESET_BIT(n) (11 + ((n + 2) % 3)) #include #include "armada-common.dtsi" @@ -276,6 +276,12 @@ CP11X_LABEL(gpio2): gpio@140 { }; }; + CP11X_LABEL(pcie_mac_reset): pcie-mac-reset@0x440268 { + compatible = "snps,dw-low-reset"; + #reset-cells = <1>; + reg = <0x440268 0x4>; + }; + CP11X_LABEL(syscon1): system-controller@400000 { compatible = "syscon", "simple-mfd"; reg = <0x400000 0x1000>; @@ -548,8 +554,7 @@ CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE { num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - marvell,mac-reset-bit-mask = ; + resets = <&CP11X_LABEL(pcie_mac_reset) CP11X_PCIEx_MAC_RESET_BIT(0)>; status = "disabled"; }; @@ -575,8 +580,7 @@ CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE { num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - marvell,mac-reset-bit-mask = ; + resets = <&CP11X_LABEL(pcie_mac_reset) CP11X_PCIEx_MAC_RESET_BIT(1)>; status = "disabled"; }; @@ -602,8 +606,7 @@ CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE { num-lanes = <1>; clock-names = "core", "reg"; clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>; - marvell,system-controller = <&CP11X_LABEL(syscon0)>; - marvell,mac-reset-bit-mask = ; + resets = <&CP11X_LABEL(pcie_mac_reset) CP11X_PCIEx_MAC_RESET_BIT(2)>; status = "disabled"; }; }; -- 2.25.1