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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241126-topic-sm8x50-pcie-global-irq-v1-2-4049cfccd073@linaro.org> On Tue, Nov 26, 2024 at 11:22:50AM +0100, Neil Armstrong wrote: > Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt > to the host CPUs. This interrupt can be used by the device driver to > identify events such as PCIe link specific events, safety events, etc... > > Hence, add it to the PCIe RC node along with the existing MSI interrupts. > > Signed-off-by: Neil Armstrong Reviewed-by: Manivannan Sadhasivam - Mani > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 ++++++++---- > 1 file changed, 8 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 9dc0ee3eb98f8711e01934e47331b99e3bb73682..44613fbe0c7f352ea0499782ca825cbe2a257aab 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1734,7 +1734,8 @@ pcie0: pcie@1c00000 { > , > , > , > - ; > + , > + ; > interrupt-names = "msi0", > "msi1", > "msi2", > @@ -1742,7 +1743,8 @@ pcie0: pcie@1c00000 { > "msi4", > "msi5", > "msi6", > - "msi7"; > + "msi7", > + "global"; > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > @@ -1850,7 +1852,8 @@ pcie1: pcie@1c08000 { > , > , > , > - ; > + , > + ; > interrupt-names = "msi0", > "msi1", > "msi2", > @@ -1858,7 +1861,8 @@ pcie1: pcie@1c08000 { > "msi4", > "msi5", > "msi6", > - "msi7"; > + "msi7", > + "global"; > #interrupt-cells = <1>; > interrupt-map-mask = <0 0 0 0x7>; > interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ > > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்