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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-434b0dbfa2csm15280125e9.17.2024.11.28.00.54.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Nov 2024 00:54:44 -0800 (PST) Date: Thu, 28 Nov 2024 09:54:44 +0100 From: Andrew Jones To: zhouquan@iscas.ac.cn Cc: anup@brainfault.org, atishp@atishpatra.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: Re: [PATCH 3/4] RISC-V: KVM: Allow Ziccrse extension for Guest/VM Message-ID: <20241128-9f7234d55cedf2afd881f82a@orel> References: <77198ab759eb01ca490f4c2199910e778b57d372.1732762121.git.zhouquan@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <77198ab759eb01ca490f4c2199910e778b57d372.1732762121.git.zhouquan@iscas.ac.cn> On Thu, Nov 28, 2024 at 11:22:07AM +0800, zhouquan@iscas.ac.cn wrote: > From: Quan Zhou > > Extend the KVM ISA extension ONE_REG interface to allow KVM user space > to detect and enable Ziccrse extension for Guest/VM. > > Signed-off-by: Quan Zhou > --- > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/vcpu_onereg.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index 340618131249..f7afb4267148 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -179,6 +179,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_SSNPM, > KVM_RISCV_ISA_EXT_SVVPTC, > KVM_RISCV_ISA_EXT_ZABHA, > + KVM_RISCV_ISA_EXT_ZICCRSE, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index 9a30a98f30bc..ed8e17da1536 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -64,6 +64,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > KVM_ISA_EXT_ARR(ZFHMIN), > KVM_ISA_EXT_ARR(ZICBOM), > KVM_ISA_EXT_ARR(ZICBOZ), > + KVM_ISA_EXT_ARR(ZICCRSE), > KVM_ISA_EXT_ARR(ZICNTR), > KVM_ISA_EXT_ARR(ZICOND), > KVM_ISA_EXT_ARR(ZICSR), > @@ -157,6 +158,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_ZFA: > case KVM_RISCV_ISA_EXT_ZFH: > case KVM_RISCV_ISA_EXT_ZFHMIN: > + case KVM_RISCV_ISA_EXT_ZICCRSE: > case KVM_RISCV_ISA_EXT_ZICNTR: > case KVM_RISCV_ISA_EXT_ZICOND: > case KVM_RISCV_ISA_EXT_ZICSR: > -- > 2.34.1 > Reviewed-by: Andrew Jones