From: Kever Yang <kever.yang@rock-chips.com>
To: heiko@sntech.de
Cc: linux-rockchip@lists.infradead.org,
Kever Yang <kever.yang@rock-chips.com>,
Conor Dooley <conor+dt@kernel.org>,
Detlev Casanova <detlev.casanova@collabora.com>,
Elaine Zhang <zhangqing@rock-chips.com>,
Finley Xiao <finley.xiao@rock-chips.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Liang Chen <cl@rock-chips.com>, Rob Herring <robh@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 3/6] dts: arm64: rockchip: Add rk3576 pcie nodes
Date: Thu, 5 Dec 2024 18:36:20 +0800 [thread overview]
Message-ID: <20241205103623.878181-4-kever.yang@rock-chips.com> (raw)
In-Reply-To: <20241205103623.878181-1-kever.yang@rock-chips.com>
rk3576 has two pcie controller, both are pcie2x1 used with
naneng-combphy.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3576.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 8938ec7c3bb4..888af56530e8 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1016,6 +1016,117 @@ qos_npu_m1ro: qos@27f22100 {
reg = <0x0 0x27f22100 0x0 0x20>;
};
+ pcie0: pcie@2a200000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ bus-range = <0x0 0xf>;
+ clocks = <&cru ACLK_PCIE0_MST>, <&cru ACLK_PCIE0_SLV>,
+ <&cru ACLK_PCIE0_DBI>, <&cru PCLK_PCIE0>,
+ <&cru CLK_PCIE0_AUX>;
+
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi", "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+ <0 0 0 2 &pcie0_intc 1>,
+ <0 0 0 3 &pcie0_intc 2>,
+ <0 0 0 4 &pcie0_intc 3>;
+ linux,pci-domain = <0>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy0_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_PHP>;
+ ranges = <0x00000800 0x0 0x20000000 0x0 0x20000000 0x0 0x00100000
+ 0x81000000 0x0 0x20100000 0x0 0x20100000 0x0 0x00100000
+ 0x82000000 0x0 0x20200000 0x0 0x20200000 0x0 0x00e00000
+ 0x83000000 0x9 0x00000000 0x9 0x00000000 0x0 0x80000000>;
+ reg = <0x0 0x2a200000 0x0 0x00010000>,
+ <0x0 0x22000000 0x0 0x00400000>,
+ <0x0 0x20000000 0x0 0x00100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ reset-names = "pipe", "p_pcie0";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ status = "disabled";
+
+ pcie0_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ pcie1: pcie@2a210000 {
+ compatible = "rockchip,rk3576-pcie", "rockchip,rk3568-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x20 0x2f>;
+ clocks = <&cru ACLK_PCIE1_MST>, <&cru ACLK_PCIE1_SLV>,
+ <&cru ACLK_PCIE1_DBI>, <&cru PCLK_PCIE1>,
+ <&cru CLK_PCIE1_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk",
+ "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "msi", "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie1_intc 0>,
+ <0 0 0 2 &pcie1_intc 1>,
+ <0 0 0 3 &pcie1_intc 2>,
+ <0 0 0 4 &pcie1_intc 3>;
+ linux,pci-domain = <0>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy1_psu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = <&power RK3576_PD_SUBPHP>;
+ ranges = <0x00000800 0x0 0x21000000 0x0 0x21000000 0x0 0x00100000
+ 0x81000000 0x0 0x21100000 0x0 0x21100000 0x0 0x00100000
+ 0x82000000 0x0 0x21200000 0x0 0x21200000 0x0 0x00e00000
+ 0x83000000 0x9 0x80000000 0x9 0x80000000 0x0 0x80000000>;
+ reg = <0x0 0x2a210000 0x0 0x00010000>,
+ <0x0 0x22400000 0x0 0x00400000>,
+ <0x0 0x21000000 0x0 0x00100000>;
+ reg-names = "apb", "dbi", "config";
+ resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ reset-names = "pipe", "p_pcie1";
+ status = "disabled";
+
+ pcie1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
gmac0: ethernet@2a220000 {
compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a";
reg = <0x0 0x2a220000 0x0 0x10000>;
--
2.25.1
next prev parent reply other threads:[~2024-12-05 12:58 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-05 10:36 [PATCH 0/6] Rockchip: add Rockchip rk3576 EVB1 board Kever Yang
2024-12-05 10:36 ` [PATCH 1/6] dt-bindings: PCI: dwc: rockchip: Add rk3576 support Kever Yang
2024-12-05 11:30 ` Heiko Stübner
2024-12-05 17:05 ` Conor Dooley
2024-12-05 10:36 ` [PATCH 2/6] dts: arm64: rockchip: Add rk3576 naneng combphy nodes Kever Yang
2024-12-05 10:36 ` Kever Yang [this message]
2024-12-05 10:36 ` [PATCH 4/6] dt-bindings: arm: rockchip: Sort for rk3568 evb Kever Yang
2024-12-05 17:14 ` Conor Dooley
2024-12-05 10:36 ` [PATCH 5/6] dt-bindings: arm: rockchip: Add rk3576 evb1 board Kever Yang
2024-12-05 17:14 ` Conor Dooley
2024-12-05 10:36 ` [PATCH 6/6] arm64: dts: " Kever Yang
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