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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?EcpjwxCKL+RxlnFuzVtEQrZkjWCvFJ2Z8jnFxYOn2T9DDIxGV45LY8MU2wFv?= =?us-ascii?Q?ltAJVJFN82g9hwXaKko6RhRH3x7G/UU7ekM41cgZaXbSLK8XgK56N/s0NhYl?= =?us-ascii?Q?gCXaStF14MW7UPLPz4ekasvFf01iWF4ue7e1TPEAlT1lPy1VVb9AIfLQB+bU?= =?us-ascii?Q?Md1WCsKt1WGduZMfeAok7l9mskkyZz9QJZkmCr2EYQ1i/n/QvpgYQJuL3C7f?= =?us-ascii?Q?nOGOSkBPaGSgU2MfByMwqlJaqy+68ALsD3HJmecrFYK4/c+cXISDVTxQhX+w?= =?us-ascii?Q?aJDu5i/V1ZzFQZZhqfbzZdIIXm1AAJIdJBC6xVqb4aNw7OJwBAZKrqu4BYvM?= =?us-ascii?Q?DyzqpbypIeUFvZfHaQeMuhjRghwa/78iiOw2nlSkvzPJxDOBb5OUi8J8qnyT?= =?us-ascii?Q?xsWSET++xLj6AW2NEj5u0e8bSvX6J8T+iM3wQYcbOfKRT5lU9GRkj0Hags4w?= =?us-ascii?Q?abFctk21rILnM+tRjPQnhVlZkv8aNcdufJsil2FAk3JIH7GEVWXXxpMV3fT5?= =?us-ascii?Q?2cBUU4hUfDZWu0jarzz40HXjCjrIW9c0TCxlpS2mgOPr2szivQo70tPzZWFh?= =?us-ascii?Q?kE+VmEEdLimDSi19aPeNbCV6UOsko83bujRB1BM5DtYJtc0wDJj1KakB1DOX?= =?us-ascii?Q?Msy4oBq7lFYXY4Zi8/sml0rfEWCBnuV/jj3rouqwvENsSYtqY6zoOppCtYSG?= =?us-ascii?Q?xU2e8M2CAh/V+68on1aSSd9DFkMqyCPVN9stDvyIfqhPV94rRmK8a44sGVqo?= =?us-ascii?Q?EhZgJBvmcX/snZu6/0cVx1ZLBsrcenFQQ2hmMAvOuJg4D6ubn4YSzdsxr1SB?= =?us-ascii?Q?VOgQZocHaZ95W4EH0wFtU7Yt9WWrD8yDr6nYMYjmx0fEfw/HJUX6HZ5LiP0N?= =?us-ascii?Q?9bDK4z74aME9IqX6Ex3dYApxYdMCFwPLSKc/xRxf0JqWhBamZw4wtX58pqSm?= =?us-ascii?Q?JNJheMJq4y+Jmd2rN+ulOkEJNh4lnhI89Pi6PxZ2sRgLeIDbTBg7NmMhiKoV?= =?us-ascii?Q?Ar/BjZ4J3gCICGQ3nzo5Kru122yrZsAHlrxpNy2CfTI9qPe45zjgldNQtzdQ?= =?us-ascii?Q?/b06ZWiEn3nw9pCE2iub5I0DJxJXDa5nNBgvODkJ91Sju9SKew90aZ4walyA?= =?us-ascii?Q?VBZrSYNruY+fGi7cBnCvAX975AfTI9/kft2c1Rp8S/RsH5rYArmbgGahEOxQ?= =?us-ascii?Q?X+zwbtbmXPVxAR8ZatCWYARY3onmCuqFukxxud1oDmZuT5qHyYZRSQhZxCaI?= =?us-ascii?Q?2KEiuVXwl/pvdJBuCIHHWXKbYZH8gsLAeLI5sQueGkJUE7VU9SZirVNd6Xoh?= =?us-ascii?Q?uHLlaGEH56qpGDQkEmSMe6hDIZxg9Uq8WuIZ4EDB7FAL1WKNble9XaBqj+nT?= =?us-ascii?Q?a2KZTjBYtjiu8cAfdFXl78IJwRhZjZ4pT+QnP8ny4/3cnXJbE3rnJvJ4qU9i?= =?us-ascii?Q?8SjWnNLpaquzbdwAxGZHcaFYwxrhgh0cFOAYDmAU1ADYKbL2Z4iLQ0V+fM54?= =?us-ascii?Q?THyrF/Xqx3/nBNl6JZFlzk+BZR5k/ShnxTmo2nlaJoTeJ3h2QDlVDmT/+bg0?= =?us-ascii?Q?p1SjGU98o7O2jmmdV1/YtUx1EF3Dm9ODaISxhi78?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: fe94e544-ddce-47ed-7d4c-08dd1a1cae52 X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6373.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2024 19:47:44.4900 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GL4/JzueIlWtQqFF/pgcO8GImhcBkBM6Jxz2lnfjMS5SZV0qAX+8MeqDJ3dUnsgp6Qur6AV1SNkw5hJYouob0w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4221 On Thu, Dec 05, 2024 at 07:40:48PM +0800, LeoLiu-oc wrote: > From: LeoLiuoc > > Call the func pci_acpi_program_hest_aer_params() for every PCIe device, > the purpose of this function is to extract register value from HEST PCIe > AER structures and program them into AER Capabilities. This function > applies to all hardware platforms that has a PCI Express AER structure > in HEST. > > Signed-off-by: LeoLiuoc > --- > drivers/pci/pci-acpi.c | 103 +++++++++++++++++++++++++++++++++++++++++ > drivers/pci/pci.h | 9 ++++ > drivers/pci/probe.c | 1 + > 3 files changed, 113 insertions(+) > > diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c > index af370628e583..6e29af8e6cc4 100644 > --- a/drivers/pci/pci-acpi.c > +++ b/drivers/pci/pci-acpi.c > @@ -19,6 +19,7 @@ > #include > #include > #include > +#include > #include "pci.h" > > /* > @@ -806,6 +807,108 @@ int pci_acpi_program_hp_params(struct pci_dev *dev) > return -ENODEV; > } > > +#ifdef CONFIG_ACPI_APEI > +/* > + * program_hest_aer_common() - configure AER common registers for Root Ports, > + * Endpoints and PCIe to PCI/PCI-X bridges > + */ > +static void program_hest_aer_common(struct acpi_hest_aer_common aer_common, > + struct pci_dev *dev, int pos) > +{ > + u32 uncor_mask; > + u32 uncor_severity; > + u32 cor_mask; > + u32 adv_cap; > + > + uncor_mask = aer_common.uncorrectable_mask; > + uncor_severity = aer_common.uncorrectable_severity; > + cor_mask = aer_common.correctable_mask; > + adv_cap = aer_common.advanced_capabilities; > + These can be done at the same time as the declarations. Same for the remaining functions. > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, uncor_mask); > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, uncor_severity); > + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, cor_mask); > + pci_write_config_dword(dev, pos + PCI_ERR_CAP, adv_cap); > +} > + > +static void program_hest_aer_root(struct acpi_hest_aer_root *aer_root, > + struct pci_dev *dev, int pos) > +{ > + u32 root_err_cmd; > + > + root_err_cmd = aer_root->root_error_command; > + > + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, root_err_cmd); > +} > + > +static void program_hest_aer_bridge(struct acpi_hest_aer_bridge *hest_aer_bridge, > + struct pci_dev *dev, int pos) > +{ > + u32 uncor_mask2; > + u32 uncor_severity2; > + u32 adv_cap2; > + > + uncor_mask2 = hest_aer_bridge->uncorrectable_mask2; > + uncor_severity2 = hest_aer_bridge->uncorrectable_severity2; > + adv_cap2 = hest_aer_bridge->advanced_capabilities2; > + > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK2, uncor_mask2); > + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER2, uncor_severity2); > + pci_write_config_dword(dev, pos + PCI_ERR_CAP2, adv_cap2); > +} > + > +static void program_hest_aer_params(struct hest_parse_aer_info info) > +{ > + struct pci_dev *dev; > + int port_type; > + int pos; > + struct acpi_hest_aer_root *hest_aer_root; > + struct acpi_hest_aer *hest_aer_endpoint; > + struct acpi_hest_aer_bridge *hest_aer_bridge; > + > + dev = info.pci_dev; > + port_type = pci_pcie_type(dev); > + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); > + if (!pos) > + return; > + > + switch (port_type) { > + case PCI_EXP_TYPE_ROOT_PORT: > + hest_aer_root = info.hest_aer_root_port; > + program_hest_aer_common(hest_aer_root->aer, dev, pos); > + program_hest_aer_root(hest_aer_root, dev, pos); > + break; > + case PCI_EXP_TYPE_ENDPOINT: > + hest_aer_endpoint = info.hest_aer_endpoint; > + program_hest_aer_common(hest_aer_endpoint->aer, dev, pos); > + break; > + case PCI_EXP_TYPE_PCI_BRIDGE: > + hest_aer_bridge = info.hest_aer_bridge; > + program_hest_aer_common(hest_aer_bridge->aer, dev, pos); > + program_hest_aer_bridge(hest_aer_bridge, dev, pos); > + break; > + default: > + return; > + break; > + } > +} > + > +int pci_acpi_program_hest_aer_params(struct pci_dev *dev) > +{ > + struct hest_parse_aer_info info = { > + .pci_dev = dev > + }; > + > + if (!pci_is_pcie(dev)) > + return -ENODEV; > + > + if (apei_hest_parse(hest_parse_pcie_aer, &info) == 1) Don't need the "== 1". > + program_hest_aer_params(info); > + > + return 0; > +} > +#endif > + > /** > * pciehp_is_native - Check whether a hotplug port is handled by the OS > * @bridge: Hotplug port to check > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 2e40fc63ba31..78bdc121c905 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -897,6 +897,15 @@ static inline void pci_save_aer_state(struct pci_dev *dev) { } > static inline void pci_restore_aer_state(struct pci_dev *dev) { } > #endif > > +#ifdef CONFIG_ACPI_APEI > +int pci_acpi_program_hest_aer_params(struct pci_dev *dev); The return value is never checked, so this can return void. > +#else > +static inline int pci_acpi_program_hest_aer_params(struct pci_dev *dev) > +{ > + return 0; > +} > +#endif > + > #ifdef CONFIG_ACPI > bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); > int pci_acpi_program_hp_params(struct pci_dev *dev); > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index 2e81ab0f5a25..33b8b46ca554 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -2304,6 +2304,7 @@ static void pci_configure_device(struct pci_dev *dev) > pci_configure_serr(dev); > > pci_acpi_program_hp_params(dev); > + pci_acpi_program_hest_aer_params(dev); This should not be called here unconditionally. OS should only write AER registers if granted permission through _OSC. It would be more appropriate to call this from pci_aer_init(). Thanks, Yazen