From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>, Vinod Koul <vkoul@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Subject: [PATCH 10/35] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4
Date: Sat, 14 Dec 2024 00:14:26 +0200 [thread overview]
Message-ID: <20241214-dpu-drop-features-v1-10-988f0662cb7e@linaro.org> (raw)
In-Reply-To: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org>
Continue migration to the MDSS-revision based checks and replace
DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 ++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
8 files changed, 27 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
index bfca56ba20ea434cb22846746cd1dcf66890679c..a070345e63ee5eaf5ef6d7b8a4cc433c20c84a12 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
@@ -32,32 +32,32 @@ static const struct dpu_ctl_cfg sm8650_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x1000,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x1000,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x1000,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 6de37c9c89995e0eecd663e6903211a453afeb56..e1eb3189aa63b88a448257976b674f5b8cbe8414 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -32,32 +32,32 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
index ab11592c204e5e6ddb8cb39df5a9248ccc60d11e..260fffff80af11f05a613b324f40c11ca0bafcbf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
@@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x290,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
}, {
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x290,
- .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+ .features = CTL_SC7280_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, {
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, {
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, {
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, {
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x290,
- .features = CTL_SM8550_MASK,
+ .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index df0af12b63703603bc6289d5bccac2940f8baa3b..6378e99452c8046f01958a96342f545c754ba8ae 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -116,9 +116,6 @@
BIT(DPU_CTL_VM_CFG) | \
BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
-#define CTL_SM8550_MASK \
- (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
-
#define INTF_SC7180_MASK \
(BIT(DPU_INTF_INPUT_CTRL) | \
BIT(DPU_INTF_STATUS_SUPPORTED) | \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index c701d18c3522393b7d18d085d6554119f27f737b..f5c40e25ce0974ffe76622b42bf8fe6db67c1a0b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -136,7 +136,6 @@ enum {
* @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
* @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
* @DPU_CTL_VM_CFG: CTL config to support multiple VMs
- * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register
* @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
* @DPU_CTL_MAX
*/
@@ -145,7 +144,6 @@ enum {
DPU_CTL_ACTIVE_CFG,
DPU_CTL_FETCH_ACTIVE,
DPU_CTL_VM_CFG,
- DPU_CTL_HAS_LAYER_EXT4,
DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
DPU_CTL_MAX
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 9a958a0c19f54c2ed2c204e314dfa8cd9e735111..5f9cd09589bb403746d48af6f8555cd224bf3195 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -535,7 +535,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);
DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);
DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);
- if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
+ if (ctx->mdss_ver->core_major_ver >= 9)
DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);
}
@@ -693,12 +693,14 @@ static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx,
* @dev: Corresponding device for devres management
* @cfg: ctl_path catalog entry for which driver object is required
* @addr: mapped register io address of MDP
+ * @mdss_ver: dpu core's major and minor versions
* @mixer_count: Number of mixers in @mixer
* @mixer: Pointer to an array of Layer Mixers defined in the catalog
*/
struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
const struct dpu_ctl_cfg *cfg,
void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver,
u32 mixer_count,
const struct dpu_lm_cfg *mixer)
{
@@ -712,6 +714,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
c->hw.log_mask = DPU_DBG_MASK_CTL;
c->caps = cfg;
+ c->mdss_ver = mdss_ver;
if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 85c6c835cc8780e6cb66f3a262d9897c91962935..f04ae0b1d986fa8f73e5bf96babfca3b4f3a0bf5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -260,6 +260,7 @@ struct dpu_hw_ctl_ops {
* @pending_wb_flush_mask: pending WB flush
* @pending_dsc_flush_mask: pending DSC flush
* @pending_cdm_flush_mask: pending CDM flush
+ * @mdss_ver: MDSS revision information
* @ops: operation list
*/
struct dpu_hw_ctl {
@@ -280,6 +281,8 @@ struct dpu_hw_ctl {
u32 pending_dsc_flush_mask;
u32 pending_cdm_flush_mask;
+ const struct dpu_mdss_version *mdss_ver;
+
/* ops */
struct dpu_hw_ctl_ops ops;
};
@@ -297,6 +300,7 @@ static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
const struct dpu_ctl_cfg *cfg,
void __iomem *addr,
+ const struct dpu_mdss_version *mdss_ver,
u32 mixer_count,
const struct dpu_lm_cfg *mixer);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index c247af03dc8ef7174eedf3d5cc267d64f17a8656..c73596ddc7edfd8065c980d203632a0707d6fede 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -134,7 +134,7 @@ int dpu_rm_init(struct drm_device *dev,
struct dpu_hw_ctl *hw;
const struct dpu_ctl_cfg *ctl = &cat->ctl[i];
- hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mixer_count, cat->mixer);
+ hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mdss_ver, cat->mixer_count, cat->mixer);
if (IS_ERR(hw)) {
rc = PTR_ERR(hw);
DPU_ERROR("failed ctl object creation: err %d\n", rc);
--
2.39.5
next prev parent reply other threads:[~2024-12-13 22:15 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-13 22:14 [PATCH 00/35] drm/msm/dpu: rework HW block feature handling Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 01/35] drm/msm/dpu: skip watchdog timer programming through TOP on >= SM8450 Dmitry Baryshkov
2025-01-15 22:01 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 02/35] drm/msm/dpu: enable DPU_WB_INPUT_CTRL for DPU 5.x Dmitry Baryshkov
2025-01-15 22:09 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 03/35] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() Dmitry Baryshkov
2025-01-16 0:22 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 04/35] drm/msm/dpu: drop INTF_SC7280_MASK Dmitry Baryshkov
2025-01-16 1:17 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 05/35] drm/msm/dpu: inline _setup_ctl_ops() Dmitry Baryshkov
2025-01-16 2:32 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 06/35] drm/msm/dpu: inline _setup_dsc_ops() Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 07/35] drm/msm/dpu: inline _setup_dspp_ops() Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 08/35] drm/msm/dpu: inline _setup_mixer_ops() Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 09/35] drm/msm/dpu: remove DSPP_SC7180_MASK Dmitry Baryshkov
2025-01-22 0:28 ` Abhinav Kumar
2025-01-22 0:47 ` Dmitry Baryshkov
2024-12-13 22:14 ` Dmitry Baryshkov [this message]
2025-01-22 0:42 ` [PATCH 10/35] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4 Abhinav Kumar
2024-12-13 22:14 ` [PATCH 11/35] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG Dmitry Baryshkov
2025-01-22 0:58 ` Abhinav Kumar
2025-01-22 9:53 ` Dmitry Baryshkov
2025-01-23 0:33 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 12/35] drm/msm/dpu: get rid of DPU_CTL_FETCH_ACTIVE Dmitry Baryshkov
2025-01-23 0:39 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 13/35] drm/msm/dpu: get rid of DPU_CTL_DSPP_SUB_BLOCK_FLUSH Dmitry Baryshkov
2025-01-23 0:54 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 14/35] drm/msm/dpu: get rid of DPU_CTL_VM_CFG Dmitry Baryshkov
2025-01-23 0:58 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 15/35] drm/msm/dpu: get rid of DPU_DATA_HCTL_EN Dmitry Baryshkov
2025-01-23 1:03 ` Abhinav Kumar
2024-12-13 22:14 ` [PATCH 16/35] drm/msm/dpu: get rid of DPU_INTF_STATUS_SUPPORTED Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 17/35] drm/msm/dpu: get rid of DPU_INTF_INPUT_CTRL Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 18/35] drm/msm/dpu: get rid of DPU_PINGPONG_DSC Dmitry Baryshkov
2025-01-23 21:32 ` Abhinav Kumar
2025-01-23 21:41 ` Abhinav Kumar
2025-01-24 5:19 ` Dmitry Baryshkov
2025-01-25 0:08 ` Abhinav Kumar
2025-01-25 1:02 ` Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 19/35] drm/msm/dpu: get rid of DPU_PINGPONG_DITHER Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 20/35] drm/msm/dpu: get rid of DPU_MDP_VSYNC_SEL Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 21/35] drm/msm/dpu: get rid of DPU_MDP_PERIPH_0_REMOVED Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 22/35] drm/msm/dpu: get rid of DPU_MDP_AUDIO_SELECT Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 23/35] drm/msm/dpu: get rid of DPU_MIXER_COMBINED_ALPHA Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 24/35] drm/msm/dpu: get rid of DPU_DIM_LAYER Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 25/35] drm/msm/dpu: get rid of DPU_DSC_HW_REV_1_2 Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 26/35] drm/msm/dpu: get rid of DPU_DSC_OUTPUT_CTRL Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 27/35] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 28/35] drm/msm/dpu: get rid of DPU_SSPP_QOS_8LVL Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 29/35] drm/msm/dpu: drop unused MDP TOP features Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 30/35] drm/msm/dpu: drop ununused PINGPONG features Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 31/35] drm/msm/dpu: drop ununused MIXER features Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 32/35] drm/msm/dpu: get rid of DPU_MIXER_SOURCESPLIT Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 33/35] drm/msm/dpu: get rid of DPU_DSC_NATIVE_42x_EN Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 34/35] drm/msm/dpu: get rid of DPU_CTL_SPLIT_DISPLAY Dmitry Baryshkov
2024-12-13 22:14 ` [PATCH 35/35] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO Dmitry Baryshkov
2025-02-17 22:10 ` (subset) [PATCH 00/35] drm/msm/dpu: rework HW block feature handling Abhinav Kumar
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