From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71F1F14AD0E for ; Wed, 18 Dec 2024 16:23:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=90.155.92.199 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734539011; cv=none; b=T5ZKBR3aYOFA3Uj/vTq7p/lWcKJJ8YlrtulfGOEn3OJCU7TD/4ZgxdeCcOdknLFHl1bcwZsOspJefCrMPC0i7L9I+I/IBScc/FerMicTUO0XdnWXs6khQmr97xAfNj4s6HEztpbYTN1QG2FbEn0c9f16AWvEfmRK1mSufBWS0H8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734539011; c=relaxed/simple; bh=7R5QUYopSZvfh3hPlVOnCe+KnDcvPaWJs3fGYJDk9QY=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=sV/k1qFR45X5aASUW5SjXJ9jqqDW++9d8Z5PrctRwqtw6av3YOwukSYrZvoesdCycYBDJjvdeF70eijAS4/3EkHGK43ZNlHRrXhPAEAEuHDLa1CrT7if8i3iZ7am2ARei/kHVKPDUKDRf9MqqYqBqYwTSUwSnmIOXAeCtcN/CBs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org; spf=none smtp.mailfrom=infradead.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b=KnkNms9K; arc=none smtp.client-ip=90.155.92.199 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=infradead.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=infradead.org header.i=@infradead.org header.b="KnkNms9K" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=EvTqf/uQhcZTFMU+4+NwnS2qbzzgoeA+rQl42NKfBmQ=; b=KnkNms9KxPraeHQ8gWwubREqj0 J8aPHhm4bHZIFBbBhs5ZEpEOpWti6OY5NuEezxbhquvZbHODyHBZE81hzUhs00ANyRc72evTmnopy iCsjHgWAA8kpIWwY8+hvE/fON+XgxoFRJH/4Agr/t3wmuM9UHQ8jVwFiuG1zLhoFp2ujqOBg11OvG iT22OpAlCuzSk5QfdqVBXgA7lOJLUT3EO+UAWZbaHZuLrgVe/zqy59ZJLbmnqEz9YtClVu9pqc08S WQIcgiFZFPRoqGxEA3r6neYJmu1rO1cVZQgaW+OFYLMZo0erpFr1jScL5mYziVikACtipouAzHSZz vFW65SSg==; Received: from 77-249-17-89.cable.dynamic.v4.ziggo.nl ([77.249.17.89] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.98 #2 (Red Hat Linux)) id 1tNwpa-00000005IoG-1EUi; Wed, 18 Dec 2024 16:23:26 +0000 Received: by noisy.programming.kicks-ass.net (Postfix, from userid 1000) id D903C30031E; Wed, 18 Dec 2024 17:23:25 +0100 (CET) Date: Wed, 18 Dec 2024 17:23:25 +0100 From: Peter Zijlstra To: "Paul E. McKenney" Cc: Daniel Xu , mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] seqlock: Use WRITE_ONCE() when updating sequence Message-ID: <20241218162325.GH2354@noisy.programming.kicks-ass.net> References: <0eaea03ecc9df536649763cfecda356fc38b6938.1734477414.git.dxu@dxuuu.xyz> <20241218103000.GK11133@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Dec 18, 2024 at 07:43:41AM -0800, Paul E. McKenney wrote: > On Wed, Dec 18, 2024 at 11:30:00AM +0100, Peter Zijlstra wrote: > > On Tue, Dec 17, 2024 at 03:17:36PM -0800, Daniel Xu wrote: > > > @@ -405,7 +405,7 @@ do { \ > > > static inline void do_raw_write_seqcount_begin(seqcount_t *s) > > > { > > > kcsan_nestable_atomic_begin(); > > > - s->sequence++; > > > + WRITE_ONCE(s->sequence, READ_ONCE(s->sequence) + 1); > > > smp_wmb(); > > > } > > > > This results in significantly worse code-gen, it will change an inc to > > memory with a load,inc,store. > > Isn't that code-generation bug in the process of being fixed? Last time I looked the compiler wasn't allowed to touch it because of all the volatile going around. Did anything change? > And, either way, given the likely cache miss, should we really care? Yeah, extra register pressure too.