From: Mark Brown <broonie@kernel.org>
To: Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Mark Brown <broonie@kernel.org>
Subject: [PATCH RFC v3 15/27] KVM: arm64: Implement SME vector length configuration
Date: Fri, 20 Dec 2024 16:46:40 +0000 [thread overview]
Message-ID: <20241220-kvm-arm64-sme-v3-15-05b018c1ffeb@kernel.org> (raw)
In-Reply-To: <20241220-kvm-arm64-sme-v3-0-05b018c1ffeb@kernel.org>
SME implements a vector length which architecturally looks very similar
to that for SVE, configured in a very similar manner. This controls the
vector length used for the ZA matrix register, and for the SVE vector
and predicate registers when in streaming mode. The only substantial
difference is that unlike SVE the architecture does not guarantee that
any particular vector length will be implemented.
Configuration for SME vector lengths is done using a virtual register as
for SVE, hook up the implementation for the virtual register. Since we
do not yet have support for any of the new SME registers stub register
access functions are provided that only allow VL configuration. These
will be extended as the SME specific registers, as for SVE.
Signed-off-by: Mark Brown <broonie@kernel.org>
---
arch/arm64/include/asm/kvm_host.h | 7 +++
arch/arm64/include/uapi/asm/kvm.h | 9 ++++
arch/arm64/kvm/guest.c | 94 +++++++++++++++++++++++++++++++--------
3 files changed, 91 insertions(+), 19 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 63e1410146f76fd584374765c04b3ba14090afdc..02f620d95f7dd2cb2b29cc25e78e7ef404cfad4c 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -708,8 +708,15 @@ struct kvm_vcpu_arch {
* low 128 bits of the SVE Z registers. When the core
* floating point code saves the register state of a task it
* records which view it saved in fp_type.
+ *
+ * If SME support is also present then it provides an
+ * alternative view of the SVE registers accessed as for the Z
+ * registers when PSTATE.SM is 1, plus an additional set of
+ * SME specific state in the matrix register ZA and LUT
+ * register ZT0.
*/
void *sve_state;
+ void *sme_state;
enum fp_type fp_type;
unsigned int max_vl[ARM64_VEC_MAX];
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 9d80d22af9d4e00204f5096fb7c8c2ee8c3646c1..efb384cf9d503007f68aad9233ba949128c94b8b 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -356,6 +356,15 @@ struct kvm_arm_counter_offset {
#define KVM_ARM64_SVE_VLS_WORDS \
((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
+/* SME registers */
+#define KVM_REG_ARM64_SME (0x17 << KVM_REG_ARM_COPROC_SHIFT)
+
+/* Vector lengths pseudo-register: */
+#define KVM_REG_ARM64_SME_VLS (KVM_REG_ARM64 | KVM_REG_ARM64_SME | \
+ KVM_REG_SIZE_U512 | 0xffff)
+#define KVM_ARM64_SME_VLS_WORDS \
+ ((KVM_ARM64_SVE_VQ_MAX - KVM_ARM64_SVE_VQ_MIN) / 64 + 1)
+
/* Bitmap feature firmware registers */
#define KVM_REG_ARM_FW_FEAT_BMAP (0x0016 << KVM_REG_ARM_COPROC_SHIFT)
#define KVM_REG_ARM_FW_FEAT_BMAP_REG(r) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c
index 5fda5dbc0c3c0ce3a20a732a68421376e54f23ca..8820cd42a27ac05874ed52c572c1dd9b29a77a1b 100644
--- a/arch/arm64/kvm/guest.c
+++ b/arch/arm64/kvm/guest.c
@@ -310,22 +310,20 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
#define vq_mask(vq) ((u64)1 << ((vq) - SVE_VQ_MIN) % 64)
#define vq_present(vqs, vq) (!!((vqs)[vq_word(vq)] & vq_mask(vq)))
-static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+static int get_vec_vls(enum vec_type vec_type, struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
{
unsigned int max_vq, vq;
u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
- if (!vcpu_has_sve(vcpu))
- return -ENOENT;
-
- if (WARN_ON(!sve_vl_valid(vcpu->arch.max_vl[ARM64_VEC_SVE])))
+ if (WARN_ON(!sve_vl_valid(vcpu->arch.max_vl[vec_type])))
return -EINVAL;
memset(vqs, 0, sizeof(vqs));
- max_vq = vcpu_sve_max_vq(vcpu);
+ max_vq = vcpu_vec_max_vq(vcpu, vec_type);
for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
- if (sve_vq_available(vq))
+ if (vq_available(vec_type, vq))
vqs[vq_word(vq)] |= vq_mask(vq);
if (copy_to_user((void __user *)reg->addr, vqs, sizeof(vqs)))
@@ -334,18 +332,13 @@ static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
return 0;
}
-static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+static int set_vec_vls(enum vec_type vec_type, struct kvm_vcpu *vcpu,
+ const struct kvm_one_reg *reg)
{
unsigned int max_vq, vq;
u64 vqs[KVM_ARM64_SVE_VLS_WORDS];
- if (!vcpu_has_sve(vcpu))
- return -ENOENT;
-
- if (kvm_arm_vcpu_vec_finalized(vcpu))
- return -EPERM; /* too late! */
-
- if (WARN_ON(vcpu->arch.sve_state))
+ if (WARN_ON(!sve_vl_valid(vcpu->arch.max_vl[vec_type])))
return -EINVAL;
if (copy_from_user(vqs, (const void __user *)reg->addr, sizeof(vqs)))
@@ -356,18 +349,18 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
if (vq_present(vqs, vq))
max_vq = vq;
- if (max_vq > sve_vq_from_vl(kvm_max_vl[ARM64_VEC_SVE]))
+ if (max_vq > sve_vq_from_vl(kvm_max_vl[vec_type]))
return -EINVAL;
/*
* Vector lengths supported by the host can't currently be
* hidden from the guest individually: instead we can only set a
- * maximum via ZCR_EL2.LEN. So, make sure the available vector
+ * maximum via xCR_EL2.LEN. So, make sure the available vector
* lengths match the set requested exactly up to the requested
* maximum:
*/
for (vq = SVE_VQ_MIN; vq <= max_vq; ++vq)
- if (vq_present(vqs, vq) != sve_vq_available(vq))
+ if (vq_present(vqs, vq) != vq_available(vec_type, vq))
return -EINVAL;
/* Can't run with no vector lengths at all: */
@@ -375,11 +368,33 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
return -EINVAL;
/* vcpu->arch.sve_state will be alloc'd by kvm_vcpu_finalize_sve() */
- vcpu->arch.max_vl[ARM64_VEC_SVE] = sve_vl_from_vq(max_vq);
+ vcpu->arch.max_vl[vec_type] = sve_vl_from_vq(max_vq);
return 0;
}
+static int get_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+ if (!vcpu_has_sve(vcpu))
+ return -ENOENT;
+
+ return get_vec_vls(ARM64_VEC_SVE, vcpu, reg);
+}
+
+static int set_sve_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+ if (!vcpu_has_sve(vcpu))
+ return -ENOENT;
+
+ if (kvm_arm_vcpu_vec_finalized(vcpu))
+ return -EPERM; /* too late! */
+
+ if (WARN_ON(vcpu->arch.sve_state))
+ return -EINVAL;
+
+ return set_vec_vls(ARM64_VEC_SVE, vcpu, reg);
+}
+
#define SVE_REG_SLICE_SHIFT 0
#define SVE_REG_SLICE_BITS 5
#define SVE_REG_ID_SHIFT (SVE_REG_SLICE_SHIFT + SVE_REG_SLICE_BITS)
@@ -533,6 +548,45 @@ static int set_sve_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
return 0;
}
+static int get_sme_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+ if (!vcpu_has_sme(vcpu))
+ return -ENOENT;
+
+ return get_vec_vls(ARM64_VEC_SME, vcpu, reg);
+}
+
+static int set_sme_vls(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+ if (!vcpu_has_sme(vcpu))
+ return -ENOENT;
+
+ if (kvm_arm_vcpu_vec_finalized(vcpu))
+ return -EPERM; /* too late! */
+
+ if (WARN_ON(vcpu->arch.sme_state))
+ return -EINVAL;
+
+ return set_vec_vls(ARM64_VEC_SME, vcpu, reg);
+}
+
+static int get_sme_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+ /* Handle the KVM_REG_ARM64_SME_VLS pseudo-reg as a special case: */
+ if (reg->id == KVM_REG_ARM64_SME_VLS)
+ return get_sme_vls(vcpu, reg);
+
+ return -EINVAL;
+}
+
+static int set_sme_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
+{
+ /* Handle the KVM_REG_ARM64_SME_VLS pseudo-reg as a special case: */
+ if (reg->id == KVM_REG_ARM64_SME_VLS)
+ return set_sme_vls(vcpu, reg);
+
+ return -EINVAL;
+}
int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
{
return -EINVAL;
@@ -775,6 +829,7 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
case KVM_REG_ARM_FW_FEAT_BMAP:
return kvm_arm_get_fw_reg(vcpu, reg);
case KVM_REG_ARM64_SVE: return get_sve_reg(vcpu, reg);
+ case KVM_REG_ARM64_SME: return get_sme_reg(vcpu, reg);
}
if (is_timer_reg(reg->id))
@@ -795,6 +850,7 @@ int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
case KVM_REG_ARM_FW_FEAT_BMAP:
return kvm_arm_set_fw_reg(vcpu, reg);
case KVM_REG_ARM64_SVE: return set_sve_reg(vcpu, reg);
+ case KVM_REG_ARM64_SME: return set_sme_reg(vcpu, reg);
}
if (is_timer_reg(reg->id))
--
2.39.5
next prev parent reply other threads:[~2024-12-20 16:51 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-20 16:46 [PATCH RFC v3 00/27] KVM: arm64: Implement support for SME in non-protected guests Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 01/27] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 02/27] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 03/27] arm64/fpsimd: Check enable bit for FA64 when saving EFI state Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 04/27] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 05/27] KVM: arm64: Introduce non-UNDEF FGT control Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 06/27] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 07/27] KVM: arm64: Convert cpacr_clear_set() to a static inline Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 08/27] KVM: arm64: Move SVE state access macros after feature test macros Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 09/27] KVM: arm64: Factor SVE guest exit handling out into a function Mark Brown
2025-01-17 11:34 ` Mark Rutland
2025-01-17 12:37 ` Mark Brown
2025-01-22 11:51 ` Marc Zyngier
2025-01-22 11:56 ` Mark Rutland
2024-12-20 16:46 ` [PATCH RFC v3 10/27] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 11/27] KVM: arm64: Document the KVM ABI for SME Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 12/27] KVM: arm64: Define internal features " Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 13/27] KVM: arm64: Rename sve_state_reg_region Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 14/27] KVM: arm64: Store vector lengths in an array Mark Brown
2024-12-20 16:46 ` Mark Brown [this message]
2024-12-20 16:46 ` [PATCH RFC v3 16/27] KVM: arm64: Add definitions for SME control register Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 17/27] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 18/27] KVM: arm64: Support SMIDR_EL1 for guests Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 19/27] KVM: arm64: Support SME priority registers Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 20/27] KVM: arm64: Provide assembly for SME state restore Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 21/27] KVM: arm64: Support Z and P registers in streaming mode Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 22/27] KVM: arm64: Expose SME specific state to userspace Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 23/27] KVM: arm64: Context switch SME state for normal guests Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 24/27] KVM: arm64: Handle SME exceptions Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 25/27] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 26/27] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2024-12-20 16:46 ` [PATCH RFC v3 27/27] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
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