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[31.30.173.28]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4366128a353sm168826375e9.42.2024.12.24.06.11.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Dec 2024 06:11:01 -0800 (PST) Date: Tue, 24 Dec 2024 15:11:00 +0100 From: Andrew Jones To: Yunhui Cui Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, conor@kernel.org, charlie@rivosinc.com, samuel.holland@sifive.com, cleger@rivosinc.com, andybnac@gmail.com, alexghiti@rivosinc.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] RISC-V: Enable cbo.clean/flush in usermode Message-ID: <20241224-2148923339996d2eed033b7e@orel> References: <20241224123946.97486-1-cuiyunhui@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20241224123946.97486-1-cuiyunhui@bytedance.com> On Tue, Dec 24, 2024 at 08:39:46PM +0800, Yunhui Cui wrote: > Enabling cbo.clean and cbo.flush in user mode makes it more > convenient to manage the cache state and achieve better performance. > > Signed-off-by: Yunhui Cui > --- > arch/riscv/kernel/cpufeature.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c0916ed318c2..60d180b98f52 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -30,6 +30,7 @@ > #define NUM_ALPHA_EXTS ('z' - 'a' + 1) > > static bool any_cpu_has_zicboz; > +static bool any_cpu_has_zicbom; > > unsigned long elf_hwcap __read_mostly; > > @@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, > pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); > return -EINVAL; > } > + > + any_cpu_has_zicbom = true; > return 0; > } > > @@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void) > current->thread.envcfg |= ENVCFG_CBZE; > else if (any_cpu_has_zicboz) > pr_warn("Zicboz disabled as it is unavailable on some harts\n"); > + > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM)) > + current->thread.envcfg |= ENVCFG_CBCFE; > + else if (any_cpu_has_zicbom) > + pr_warn("Zicbom disabled as it is unavailable on some harts\n"); > } > > #ifdef CONFIG_RISCV_ALTERNATIVE > -- > 2.39.2 > This looks good, so Reviewed-by: Andrew Jones but, as a separate patch, we should also provide hwprobe support like zicboz has, i.e. add ZICBOM to the IMA ext0 key and add a key for the zicbom block size. And then, as another patch, add a test_zicbom() function to tools/testing/selftests/riscv/hwprobe/cbo.c. Thanks, drew