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Mon, 30 Dec 2024 06:16:47 -0800 (PST) Date: Mon, 30 Dec 2024 19:46:43 +0530 From: Manivannan Sadhasivam To: Vivek Pernamitta Cc: quic_krichai@quicinc.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5] bus: mhi: host: pci_generic: Add support for QDU100 device Message-ID: <20241230141643.rkbaway3dwlwwbhm@thinkpad> References: <20241212-qdu100_us-v5-1-3349fb23512a@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241212-qdu100_us-v5-1-3349fb23512a@quicinc.com> On Thu, Dec 12, 2024 at 05:27:27PM +0530, Vivek Pernamitta wrote: > Add MHI controller configuration for QDU100 device. > > The Qualcomm X100 5G RAN Accelerator card is designed to enhance Open vRAN > servers by offloading CPUs from intensive 5G baseband functions. > > Link: https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf > > Signed-off-by: Vivek Pernamitta Reviewed-by: Manivannan Sadhasivam - Mani > --- > changes from V4: > - Updated QDU100 VID as per order in mhi_pci_id_table. > - Link to v4: https://lore.kernel.org/r/20241209-qdu100_us-v4-1-f9010b2a09a2@quicinc.com > > changes from V3: > - Removed IP_SW1 and IP_SW2 support currently, will add once > SW_IP1/2 channels support are added to mhi-net driver. > - Removed qdu100 edl images, as EDL images are not needed. > - Added space inbetween kernel_ulong_t and mhi_qcom_qdu100_info. > - QDU100 XBL FW images were pushed to linux-firmware git repo > https://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git/tree/qcom/qdu100 > > changes from V2: > - updated commit text. > > changes from V1: > - Changing naming convention from modem_qcom_qdu100* > to mhi_qcom_qdu100*. > - Updated commit text. > - Fixed and corrected by passing mhi_pci_dev_info struct > instead of mhi_controller_config. > --- > > --- > drivers/bus/mhi/host/pci_generic.c | 55 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 55 insertions(+) > > diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c > index 07645ce2119a71c9277356e962252b840379cd81..aa5118dbe2e5de3f3d13a168ebe2d3d2d5930295 100644 > --- a/drivers/bus/mhi/host/pci_generic.c > +++ b/drivers/bus/mhi/host/pci_generic.c > @@ -245,6 +245,58 @@ struct mhi_pci_dev_info { > .channel = ch_num, \ > } > > +static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = { > + MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2), > + MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2), > + MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1), > + MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1), > + MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3), > + MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3), > + MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3), > + MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4), > + MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4), > + MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4), > + MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4), > + MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4), > + MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4), > + MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5), > + MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5), > +}; > + > +static struct mhi_event_config mhi_qcom_qdu100_events[] = { > + /* first ring is control+data ring */ > + MHI_EVENT_CONFIG_CTRL(0, 64), > + /* SAHARA dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(1, 256), > + /* Software channels dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(2, 64), > + MHI_EVENT_CONFIG_SW_DATA(3, 256), > + MHI_EVENT_CONFIG_SW_DATA(4, 256), > + /* Software IP channels dedicated event ring */ > + MHI_EVENT_CONFIG_SW_DATA(5, 512), > + MHI_EVENT_CONFIG_SW_DATA(6, 512), > + MHI_EVENT_CONFIG_SW_DATA(7, 512), > +}; > + > +static const struct mhi_controller_config mhi_qcom_qdu100_config = { > + .max_channels = 128, > + .timeout_ms = 120000, > + .num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels), > + .ch_cfg = mhi_qcom_qdu100_channels, > + .num_events = ARRAY_SIZE(mhi_qcom_qdu100_events), > + .event_cfg = mhi_qcom_qdu100_events, > +}; > + > +static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = { > + .name = "qcom-qdu100", > + .fw = "qcom/qdu100/xbl_s.melf", > + .edl_trigger = true, > + .config = &mhi_qcom_qdu100_config, > + .bar_num = MHI_PCI_DEFAULT_BAR_NUM, > + .dma_data_width = 32, > + .sideband_wake = false, > +}; > + > static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = { > MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1), > MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1), > @@ -742,6 +794,9 @@ static const struct pci_device_id mhi_pci_id_table[] = { > .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info }, > { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309), > .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info }, > + /* QDU100, x100-DU */ > + { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601), > + .driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info }, > { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */ > .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info }, > { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */ > > --- > base-commit: 28955f4fa2823e39f1ecfb3a37a364563527afbc > change-id: 20241127-qdu100_us-abd7d1613c8b > > Best regards, > -- > Vivek Pernamitta > -- மணிவண்ணன் சதாசிவம்