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charset=us-ascii Content-Disposition: inline Hi Niklas, First bad commit (maybe != root cause): tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: ccb98ccef0e543c2bd4ef1a72270461957f3d8d0 commit: 84e30b878aed9353d74904d72cba9f968ae5675b PCI: dw-rockchip: Use pci_epc_init_notify() directly date: 6 months ago config: alpha-randconfig-r054-20241231 (https://download.01.org/0day-ci/archive/20241231/202412312343.najrW1Db-lkp@intel.com/config) compiler: alpha-linux-gcc (GCC) 14.2.0 If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202412312343.najrW1Db-lkp@intel.com/ cocci warnings: (new ones prefixed by >>) >> drivers/pci/controller/dwc/pcie-dw-rockchip.c:454:2-9: line 454 is redundant because platform_get_irq() already prints an error vim +454 drivers/pci/controller/dwc/pcie-dw-rockchip.c 49a0925d173324 Niklas Cassel 2024-06-07 441 e242f26f6320e3 Niklas Cassel 2024-06-07 442 static int rockchip_pcie_configure_ep(struct platform_device *pdev, e242f26f6320e3 Niklas Cassel 2024-06-07 443 struct rockchip_pcie *rockchip) e242f26f6320e3 Niklas Cassel 2024-06-07 444 { e242f26f6320e3 Niklas Cassel 2024-06-07 445 struct device *dev = &pdev->dev; e242f26f6320e3 Niklas Cassel 2024-06-07 446 int irq, ret; e242f26f6320e3 Niklas Cassel 2024-06-07 447 u32 val; e242f26f6320e3 Niklas Cassel 2024-06-07 448 e242f26f6320e3 Niklas Cassel 2024-06-07 449 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP)) e242f26f6320e3 Niklas Cassel 2024-06-07 450 return -ENODEV; e242f26f6320e3 Niklas Cassel 2024-06-07 451 e242f26f6320e3 Niklas Cassel 2024-06-07 452 irq = platform_get_irq_byname(pdev, "sys"); e242f26f6320e3 Niklas Cassel 2024-06-07 453 if (irq < 0) { e242f26f6320e3 Niklas Cassel 2024-06-07 @454 dev_err(dev, "missing sys IRQ resource\n"); e242f26f6320e3 Niklas Cassel 2024-06-07 455 return irq; e242f26f6320e3 Niklas Cassel 2024-06-07 456 } e242f26f6320e3 Niklas Cassel 2024-06-07 457 e242f26f6320e3 Niklas Cassel 2024-06-07 458 ret = devm_request_threaded_irq(dev, irq, NULL, e242f26f6320e3 Niklas Cassel 2024-06-07 459 rockchip_pcie_ep_sys_irq_thread, e242f26f6320e3 Niklas Cassel 2024-06-07 460 IRQF_ONESHOT, "pcie-sys", rockchip); e242f26f6320e3 Niklas Cassel 2024-06-07 461 if (ret) { e242f26f6320e3 Niklas Cassel 2024-06-07 462 dev_err(dev, "failed to request PCIe sys IRQ\n"); e242f26f6320e3 Niklas Cassel 2024-06-07 463 return ret; e242f26f6320e3 Niklas Cassel 2024-06-07 464 } e242f26f6320e3 Niklas Cassel 2024-06-07 465 e242f26f6320e3 Niklas Cassel 2024-06-07 466 /* LTSSM enable control mode */ e242f26f6320e3 Niklas Cassel 2024-06-07 467 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE); e242f26f6320e3 Niklas Cassel 2024-06-07 468 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL); e242f26f6320e3 Niklas Cassel 2024-06-07 469 e242f26f6320e3 Niklas Cassel 2024-06-07 470 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE, e242f26f6320e3 Niklas Cassel 2024-06-07 471 PCIE_CLIENT_GENERAL_CONTROL); e242f26f6320e3 Niklas Cassel 2024-06-07 472 e242f26f6320e3 Niklas Cassel 2024-06-07 473 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops; e242f26f6320e3 Niklas Cassel 2024-06-07 474 rockchip->pci.ep.page_size = SZ_64K; e242f26f6320e3 Niklas Cassel 2024-06-07 475 e242f26f6320e3 Niklas Cassel 2024-06-07 476 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); e242f26f6320e3 Niklas Cassel 2024-06-07 477 e242f26f6320e3 Niklas Cassel 2024-06-07 478 ret = dw_pcie_ep_init(&rockchip->pci.ep); e242f26f6320e3 Niklas Cassel 2024-06-07 479 if (ret) { e242f26f6320e3 Niklas Cassel 2024-06-07 480 dev_err(dev, "failed to initialize endpoint\n"); e242f26f6320e3 Niklas Cassel 2024-06-07 481 return ret; e242f26f6320e3 Niklas Cassel 2024-06-07 482 } e242f26f6320e3 Niklas Cassel 2024-06-07 483 e242f26f6320e3 Niklas Cassel 2024-06-07 484 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep); e242f26f6320e3 Niklas Cassel 2024-06-07 485 if (ret) { e242f26f6320e3 Niklas Cassel 2024-06-07 486 dev_err(dev, "failed to initialize DWC endpoint registers\n"); e242f26f6320e3 Niklas Cassel 2024-06-07 487 dw_pcie_ep_deinit(&rockchip->pci.ep); e242f26f6320e3 Niklas Cassel 2024-06-07 488 return ret; e242f26f6320e3 Niklas Cassel 2024-06-07 489 } e242f26f6320e3 Niklas Cassel 2024-06-07 490 84e30b878aed93 Niklas Cassel 2024-06-22 491 pci_epc_init_notify(rockchip->pci.ep.epc); e242f26f6320e3 Niklas Cassel 2024-06-07 492 e242f26f6320e3 Niklas Cassel 2024-06-07 493 /* unmask DLL up/down indicator and hot reset/link-down reset */ e242f26f6320e3 Niklas Cassel 2024-06-07 494 rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC); e242f26f6320e3 Niklas Cassel 2024-06-07 495 e242f26f6320e3 Niklas Cassel 2024-06-07 496 return ret; e242f26f6320e3 Niklas Cassel 2024-06-07 497 } e242f26f6320e3 Niklas Cassel 2024-06-07 498 :::::: The code at line 454 was first introduced by commit :::::: e242f26f6320e30e77e0455473a9d7f037ddb8a0 PCI: dw-rockchip: Add endpoint mode support :::::: TO: Niklas Cassel :::::: CC: Bjorn Helgaas -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki