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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38a1c89e2dfsm36764411f8f.74.2025.01.01.13.16.37 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 01 Jan 2025 13:16:37 -0800 (PST) Date: Wed, 1 Jan 2025 21:16:37 +0000 From: David Laight To: Alexander Usyskin Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , Thomas =?UTF-8?B?SGVsbHN0csO2bQ==?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa , Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 06/11] mtd: intel-dg: align 64bit read and write Message-ID: <20250101211637.709b65e1@dsl-u17-10> In-Reply-To: <20250101164119.000d2bd4@dsl-u17-10> References: <20250101153925.865703-1-alexander.usyskin@intel.com> <20250101153925.865703-7-alexander.usyskin@intel.com> <20250101164119.000d2bd4@dsl-u17-10> X-Mailer: Claws Mail 3.16.0 (GTK+ 2.24.32; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 1 Jan 2025 16:41:19 +0000 David Laight wrote: > On Wed, 1 Jan 2025 17:39:20 +0200 > Alexander Usyskin wrote: > > > GSC NVM controller HW errors on quad access overlapping 1K border. > > Align 64bit read and write to avoid readq/writeq over 1K border. > > > > Acked-by: Miquel Raynal > > Signed-off-by: Alexander Usyskin > > --- > > drivers/mtd/devices/mtd-intel-dg.c | 35 ++++++++++++++++++++++++++++++ > > 1 file changed, 35 insertions(+) > > > > diff --git a/drivers/mtd/devices/mtd-intel-dg.c b/drivers/mtd/devices/mtd-intel-dg.c > > index 76ef7198fff8..230bf444b7fe 100644 > > --- a/drivers/mtd/devices/mtd-intel-dg.c > > +++ b/drivers/mtd/devices/mtd-intel-dg.c > > @@ -238,6 +238,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region, > > len_s -= to_shift; > > } > > > > + if (!IS_ALIGNED(to, sizeof(u64)) && > > + ((to ^ (to + len_s)) & GENMASK(31, 10))) { That might as well be the easier to understand: if ((to & 7) && (to & 1023) + len_s > 1024) Replacing (add, xor, and) with (and, add, cmp) is much the same even without the decrement. David