From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4AE8F6FB0 for ; Thu, 2 Jan 2025 13:26:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.249 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735824413; cv=none; b=UHYHN3O5DwM0CQAtJgIe+PmVhpr6y6xJxPFlIo7pDptCj5ClhOPSo1MiEVjq1BvHwrSAkJKE6KUF7be1nmluF8JnZAneQ6lBU50D4GcNv0bTYU/4jJtUZtguSWijvEp2TVJ0n3akARLdBuk9OklLSBg6y6ZHjpVJpcmwdJvj+xA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1735824413; c=relaxed/simple; bh=MFJFFA4X38tKgaCOzlBrW87R0ThAtRq14qF1imCi7Hw=; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=pSlN9brHX4x8Bu0+jAL6G4SgXfsGqdcoi3k/Ia9V66WrKJGFgnPrlG0ec4SBuqrcUk9Af8B8feovibMIL1d77uB9BESCj0iQvpuixku4jlMwEvq6eyY6mywjIZoS7/s2P/PMTR3ibOYf6non7S8GhtulVugGWE/AgqKcBHnRHx0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=f5vpED8j; arc=none smtp.client-ip=198.47.23.249 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="f5vpED8j" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 502DQT0K055293; Thu, 2 Jan 2025 07:26:29 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1735824390; bh=Jr9h36oY869ZaVN1opg3awIyzL1sLfK+U4JefczpWKg=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=f5vpED8j6HiHdugP0bDrgMPPHixbIpCcuPXT+FjhcyyPM4GoaVTnU2qNxzadxxgLm Nx7yrzunCENC6hCruvLuJr6s+pPkwBSNNygBXJcaT1mgZ4NTUX4BWS/zjYzssyJG0B 42+PQ0DWouY/hQ7puHmlmUr2A0YI3b3b3brRKd08= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 502DQTxd046151 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 2 Jan 2025 07:26:29 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 2 Jan 2025 07:26:29 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 2 Jan 2025 07:26:29 -0600 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 502DQTKJ125284; Thu, 2 Jan 2025 07:26:29 -0600 Date: Thu, 2 Jan 2025 07:26:29 -0600 From: Nishanth Menon To: Marc Zyngier CC: Guillaume La Roque , Catalin Marinas , Will Deacon , Thomas Gleixner , Tero Kristo , Santosh Shilimkar , , , , Mattijs Korpershoek , Kevin Hilman , Nicolas Frayer Subject: Re: [PATCH v4 0/2] irqchip: Kconfig: Add module support for TI inta/intr Message-ID: <20250102132629.qluai4vzvwotrn43@fernlike> References: <20241224-timodules-v4-0-c5e010f58e2c@baylibre.com> <20250102124413.wwbfzomjzedbqges@thinness> <86cyh5pdk6.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <86cyh5pdk6.wl-maz@kernel.org> X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 13:09-20250102, Marc Zyngier wrote: > On Thu, 02 Jan 2025 12:44:13 +0000, > Nishanth Menon wrote: > > > > On 20:36-20241224, Guillaume La Roque wrote: > > > Added module support for TI interrupt aggregator and interrupt router > > > drivers. Default value for both drivers is ARCH_K3 and the interrupt > > > aggregator depends on ARCH_K3 as it contains 64 bit only ops. > > > Tested allmodconfig builds with ARCH=arm and ARCH=arm64. > > > > > > Changes in v4: > > > - Rework commit message and title > > > - Add depends on in Kconfig frivers > > > - Link to v3: https://lore.kernel.org/r/20241016-timodules-v3-0-fa71091ade98@baylibre.com > > > > > > Changes in v3: > > > - Add MODULE_LICENSE in drivers > > > > > > Changes in v2: > > > - Added depends on ARCH_K3 for the interrupt aggregator driver as it > > > uses > > > 64 bit ops > > > > > > Signed-off-by: Guillaume La Roque > > > --- > > > Nicolas Frayer (2): > > > irqchip/ti-sci-intr: add module build support > > > irqchip/ti-sci-inta : Add module build support > > > > > > arch/arm64/Kconfig.platforms | 2 -- > > > drivers/irqchip/Kconfig | 6 ++++-- > > > drivers/irqchip/irq-ti-sci-inta.c | 1 + > > > drivers/irqchip/irq-ti-sci-intr.c | 1 + > > > 4 files changed, 6 insertions(+), 4 deletions(-) > > > --- > > > base-commit: 8faabc041a001140564f718dabe37753e88b37fa > > > change-id: 20241016-timodules-174770215dd8 > > > > > > Best regards, > > > -- > > > Guillaume La Roque > > > > > > > Reviewed-by: Nishanth Menon > > > > Marc, Can this go via your tree? > > I'm only looking after the ARM GICs these days, and not anything else. > Hopefully Thomas will look into it. Thanks Marc. Thomas, would like to know if you'd pick this up, else, I can take this series via my tree and send via SoC maintainers, since I am marked as the maintainer for the files. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D