From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E07714C59B for ; Sun, 5 Jan 2025 16:35:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.170 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736094921; cv=none; b=MkmX65SAaW2m7nEIxFW5txu9pupshXgulJqcpBK1W7ZCbDotlQHmt1hskAbKV38Kvo2AC67KDdgQScdvhxf2jBls0i5AYV1CGuF3biWeNik66llSYD5f/28Nmt7ExflQlh87Ujg1YeeoFBA+PAGZKUF7CYspHqLYM98eH5CQoUw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736094921; c=relaxed/simple; bh=W8n4UV6+W1kcJ9PGinQ/CjgG6MkwYDyuasni3ltxRO0=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=FwME9/i7Y6tIBFVBhl261qr2to9zP9N53DEVH6Ydp/P2SRuWquUUscw7Gix03duaL+6LfDh0m3vXjUbB+nIas/WxVWWSPvFvRJWmOU6COJYed413nZ7zEDfDY6bahNR0ECl0liV24N0Ig1QugZx4lNZMrdS008BZeQS6AxTubj8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=i0VuDodx; arc=none smtp.client-ip=209.85.214.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="i0VuDodx" Received: by mail-pl1-f170.google.com with SMTP id d9443c01a7336-219f8263ae0so147063385ad.0 for ; Sun, 05 Jan 2025 08:35:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1736094918; x=1736699718; darn=vger.kernel.org; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=PnREJXO8gdOnlDXn6hPd7bSDzdru7IQfI4OFlA05/Zk=; b=i0VuDodxftT9iVhyH5DlZjIW4/9meupkBgQgSN8wpOa8upkfz2qe+wzAuFemBrDUdy Hp0o33L5SwSnnLZKM9a0bzXm4u1/LGG6YS3DK07kKx6kzh35eynv68Nk5Wa2Bn2roDfv YZeRZoU+I/CMZct6W9de5RAAwhCDwsfnzNrpyilBdSK3ODF+/2TlKSKC2K3hqtnE4zt3 OybOS9sMkLahJVc71smniNyZkBbfzjh4LJCLnSYgNVlb2yq49P4uZVj6HihRY4qqk6it 9kDOxf1NuyXYnnTd/z/LUNWqnPx/1nVuRr67kdq686L9OMgDK2trZl+N/hJ6bcAi14IA J3mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1736094918; x=1736699718; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=PnREJXO8gdOnlDXn6hPd7bSDzdru7IQfI4OFlA05/Zk=; b=sGtqnjmNRUmyB6XhZMmg3WdDENCWnWbbymKlEdFpA/1p7aNOtdFLjelRoskcZalK5l yM7OuQti3eKLhc9ACFkaWNrlBbMaiyqVcAVl/wDYfGjYSQhZRH97/J6/NglqOhiaKFbr oPhqtcmAhz44DmbG+TmpubjGYGbGO8NnYViI31jZLuT5cUYNCFcUOBrQ+Z6YfBypgKT2 D7KHxyZ7nsn4AFYQ7h9r53rjrHTV32qpWibIr9rxbeG66zFGO+wQPCLnwpwkcD8QgCR7 ZmgCnPrjUpFMuDInFRem5kIg+ak46oJNt8af8Zqjp4C0M5T3HLNpDXg2txQl1HwZJWRV SVyA== X-Forwarded-Encrypted: i=1; AJvYcCVza4leNUtXxDGrh4bJUrTJ1I6lHFRd3WkNYmi0CIGejIaj7xRAo1z2p+ZZF4UJwmteCnV1Wj2s7V6CGeY=@vger.kernel.org X-Gm-Message-State: AOJu0YyQbt/2T9K/nVe0VaBCVIt9xtBvV098oZT/nv3f1LDoJMA9JxGw 4ydXspeVFgjr/WS5+NfanX+rg78Z/0gqacazaZKl3qFVzf4NEHLCA34MAjhZdQ== X-Gm-Gg: ASbGncuvdjge1p3YhipkX9qQFg+hRV8WGQAVHul9hkD02GQYi9ensq3U1zZQEzDHIqW To9kKYQf7sCesD5F5FufLw6hfcQ/+6Elnm7x7rBYBwv+KR+RHRX3Io17Oy1XbT2TCwU5XEyFAvw n8JffeluDHIUt9lNCjPNJcULqio3x5VAW6qHHLCEgkeJ4sUTZj42pYf00xq9eJF/EY6f/YmCv9b cPvI7bOE/0bfF1ts93CNrWEnGRy1tTsqgYgTwEIAgP9GwY5++gPZHJXW/CDbc7SQt2c6A== X-Google-Smtp-Source: AGHT+IEOtAp4w31CjTLB1aFWoVsatu6IG9r4c5kd2CVIdLrHft5tD4dMe9HJZQJaorB/J3Udvac1sQ== X-Received: by 2002:a17:903:2cc:b0:216:2e5e:971d with SMTP id d9443c01a7336-219e70dc3f7mr692735935ad.51.1736094918605; Sun, 05 Jan 2025 08:35:18 -0800 (PST) Received: from thinkpad ([117.193.213.165]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-219dc9cde72sm277254345ad.130.2025.01.05.08.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 05 Jan 2025 08:35:18 -0800 (PST) Date: Sun, 5 Jan 2025 22:05:11 +0530 From: Manivannan Sadhasivam To: Anand Moon Cc: Niklas Cassel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] PCI: dw-rockchip: Enable async probe by default Message-ID: <20250105163511.rwer5pl6tevw4zp2@thinkpad> References: <20240809073610.2517-1-linux.amoon@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Fri, Jan 03, 2025 at 08:59:51PM +0530, Anand Moon wrote: > Hi Niklas > > On Fri, 3 Jan 2025 at 20:40, Niklas Cassel wrote: > > > > On Fri, Jan 03, 2025 at 08:36:18PM +0530, Anand Moon wrote: > > > > > > > > > > We need to enable the GMAC PHY and reset it using the proper GPIO pin > > > > > (PCIE_PERST_L). > > > > > Please refer to the schematic for more details. > > > > > > > > The PERST# GPIO is already asserted + deasserted from the PCIe Root Complex > > > > (host) driver: > > > > https://github.com/torvalds/linux/blob/v6.13-rc5/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L191-L206 > > > > > > > > which will cause the endpoint device (a RTL8125 NIC in this case) > > > > to be reset during bootup. > > > > > > > Thanks for letting me know. It seems like a workaround. > > > I'll try to disable this and test it again. > > > > > > My point is that we haven't enabled the GMAC PHY (device nodes) > > > and must properly reset the GMAC. > > > > > > We're relying on the code above hack to do that job. > > > > I do not think it is a hack. > > > > If you look in most PCIe controller drivers, they toggle PERST before > > enumerating the bus: > > $ git grep gpiod_set_value drivers/pci/controller/ > > > > Ok, understood. However, we have multiple reset lines per controller, > so the PCIe driver will reset these lines using gpiod_set_value. > > PCIE30X4_PERSTn_M1_L > PCIE30x1_0_PERSTn_M1_L > PCIE_PERST_L PERST# gpio is unique per controller instance and will be asserted/deasserted by the PCIe controller driver itself. Endpoint drivers should not touch these. And most of the PCIe endpoint devices do not need to be described in devicetree as PCIe is a discoverable bus. But we do define some of them if they require any special board configuration. - Mani -- மணிவண்ணன் சதாசிவம்