From: James Clark <james.clark@linaro.org>
To: maz@kernel.org, kvmarm@lists.linux.dev, oliver.upton@linux.dev,
suzuki.poulose@arm.com, coresight@lists.linaro.org
Cc: James Clark <james.clark@arm.com>,
Mark Brown <broonie@kernel.org>,
James Clark <james.clark@linaro.org>,
Joey Gouly <joey.gouly@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Mike Leach <mike.leach@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Mark Rutland <mark.rutland@arm.com>,
Shiqi Liu <shiqiliu@hust.edu.cn>,
James Morse <james.morse@arm.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Fuad Tabba <tabba@google.com>,
"Rob Herring (Arm)" <robh@kernel.org>,
Raghavendra Rao Ananta <rananta@google.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v10 06/10] arm64/sysreg/tools: Move TRFCR definitions to sysreg
Date: Tue, 7 Jan 2025 11:32:43 +0000 [thread overview]
Message-ID: <20250107113252.260631-7-james.clark@linaro.org> (raw)
In-Reply-To: <20250107113252.260631-1-james.clark@linaro.org>
From: James Clark <james.clark@arm.com>
Convert TRFCR to automatic generation. Add separate definitions for ELx
and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous
definition so no code change is required.
Also add TRFCR_EL12 which will start to be used in a later commit.
Unfortunately, to avoid breaking the Perf build with duplicate
definition errors, the tools copy of the sysreg.h header needs to be
updated at the same time rather than the usual second commit. This is
because the generated version of sysreg
(arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared
and tools/ does not have its own copy.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Clark <james.clark@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
---
arch/arm64/include/asm/sysreg.h | 12 ---------
arch/arm64/tools/sysreg | 36 +++++++++++++++++++++++++++
tools/arch/arm64/include/asm/sysreg.h | 12 ---------
3 files changed, 36 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b8303a83c0bf..808f65818b91 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -283,8 +283,6 @@
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
-#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
-
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
-#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
-#define TRFCR_ELx_TS_SHIFT 5
-#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_EL2_CX BIT(3)
-#define TRFCR_ELx_ExTRE BIT(1)
-#define TRFCR_ELx_E0TRE BIT(0)
-
/* GIC Hypervisor interface registers */
/* ICH_MISR_EL2 bit definitions */
#define ICH_MISR_EOI (1 << 0)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4ba167089e2a..ef8a06e180b3 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1997,6 +1997,22 @@ Sysreg CPACR_EL1 3 0 1 0 2
Fields CPACR_ELx
EndSysreg
+SysregFields TRFCR_ELx
+Res0 63:7
+UnsignedEnum 6:5 TS
+ 0b0001 VIRTUAL
+ 0b0010 GUEST_PHYSICAL
+ 0b0011 PHYSICAL
+EndEnum
+Res0 4:2
+Field 1 ExTRE
+Field 0 E0TRE
+EndSysregFields
+
+Sysreg TRFCR_EL1 3 0 1 2 1
+Fields TRFCR_ELx
+EndSysreg
+
Sysreg SMPRI_EL1 3 0 1 2 4
Res0 63:4
Field 3:0 PRIORITY
@@ -2546,6 +2562,22 @@ Field 1 ICIALLU
Field 0 ICIALLUIS
EndSysreg
+Sysreg TRFCR_EL2 3 4 1 2 1
+Res0 63:7
+UnsignedEnum 6:5 TS
+ 0b0000 USE_TRFCR_EL1_TS
+ 0b0001 VIRTUAL
+ 0b0010 GUEST_PHYSICAL
+ 0b0011 PHYSICAL
+EndEnum
+Res0 4
+Field 3 CX
+Res0 2
+Field 1 E2TRE
+Field 0 E0HTRE
+EndSysreg
+
+
Sysreg HDFGRTR_EL2 3 4 3 1 4
Field 63 PMBIDR_EL1
Field 62 nPMSNEVFR_EL1
@@ -2956,6 +2988,10 @@ Sysreg ZCR_EL12 3 5 1 2 0
Fields ZCR_ELx
EndSysreg
+Sysreg TRFCR_EL12 3 5 1 2 1
+Fields TRFCR_ELx
+EndSysreg
+
Sysreg SMCR_EL12 3 5 1 2 6
Fields SMCR_ELx
EndSysreg
diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
index 345e81e0d2b3..150416682e2c 100644
--- a/tools/arch/arm64/include/asm/sysreg.h
+++ b/tools/arch/arm64/include/asm/sysreg.h
@@ -283,8 +283,6 @@
#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
-#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
-
#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
#define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
#define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
#define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
-#define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
#define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
#define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
#define SYS_MPIDR_SAFE_VAL (BIT(31))
-#define TRFCR_ELx_TS_SHIFT 5
-#define TRFCR_ELx_TS_MASK ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_VIRTUAL ((0x1UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_GUEST_PHYSICAL ((0x2UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_PHYSICAL ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_EL2_CX BIT(3)
-#define TRFCR_ELx_ExTRE BIT(1)
-#define TRFCR_ELx_E0TRE BIT(0)
-
/* GIC Hypervisor interface registers */
/* ICH_MISR_EL2 bit definitions */
#define ICH_MISR_EOI (1 << 0)
--
2.34.1
next prev parent reply other threads:[~2025-01-07 11:34 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-07 11:32 [PATCH v10 00/10] kvm/coresight: Support exclude guest and exclude host James Clark
2025-01-07 11:32 ` [PATCH v10 01/10] KVM: arm64: Drop MDSCR_EL1_DEBUG_MASK James Clark
2025-01-07 11:32 ` [PATCH v10 02/10] KVM: arm64: Get rid of __kvm_get_mdcr_el2() and related warts James Clark
2025-01-07 11:32 ` [PATCH v10 03/10] KVM: arm64: Track presence of SPE/TRBE in kvm_host_data instead of vCPU James Clark
2025-01-07 11:32 ` [PATCH v10 04/10] arm64/sysreg: Add a comment that the sysreg file should be sorted James Clark
2025-01-12 12:49 ` Marc Zyngier
2025-01-13 15:43 ` James Clark
2025-01-13 16:49 ` Marc Zyngier
2025-01-13 17:02 ` Mark Brown
2025-01-14 18:16 ` Rob Herring
2025-01-14 19:45 ` Mark Brown
2025-01-15 10:43 ` James Clark
2025-01-15 13:00 ` Mark Brown
2025-01-07 11:32 ` [PATCH v10 05/10] tools: arm64: Update sysreg.h header files James Clark
2025-01-07 11:32 ` James Clark [this message]
2025-01-12 12:58 ` [PATCH v10 06/10] arm64/sysreg/tools: Move TRFCR definitions to sysreg Marc Zyngier
2025-01-12 13:58 ` Marc Zyngier
2025-01-13 16:29 ` James Clark
2025-01-07 11:32 ` [PATCH v10 07/10] coresight: trbe: Remove redundant disable call James Clark
2025-01-07 11:32 ` [PATCH v10 08/10] KVM: arm64: coresight: Give TRBE enabled state to KVM James Clark
2025-01-07 11:32 ` [PATCH v10 09/10] KVM: arm64: Support trace filtering for guests James Clark
2025-01-07 11:32 ` [PATCH v10 10/10] coresight: Pass guest TRFCR value to KVM James Clark
2025-01-12 14:02 ` (subset) [PATCH v10 00/10] kvm/coresight: Support exclude guest and exclude host Marc Zyngier
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