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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab2c9564848sm490993366b.125.2025.01.13.04.41.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jan 2025 04:41:20 -0800 (PST) Date: Mon, 13 Jan 2025 13:41:19 +0100 From: Andrew Jones To: yunhui cui Cc: alexghiti@rivosinc.com, andybnac@gmail.com, aou@eecs.berkeley.edu, charlie@rivosinc.com, cleger@rivosinc.com, conor.dooley@microchip.com, conor@kernel.org, corbet@lwn.net, evan@rivosinc.com, jesse@rivosinc.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-riscv@lists.infradead.org, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel.holland@sifive.com, shuah@kernel.org Subject: Re: [External] Re: [PATCH v3 2/3] RISC-V: hwprobe: Expose Zicbom extension and its block size Message-ID: <20250113-da3ae77c9eb1342ac19ec59c@orel> References: <20250113083635.73826-1-cuiyunhui@bytedance.com> <20250113083635.73826-2-cuiyunhui@bytedance.com> <20250113-65f27ad723c0f6585f86ae7f@orel> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Mon, Jan 13, 2025 at 07:29:39PM +0800, yunhui cui wrote: > Hi drew, > > On Mon, Jan 13, 2025 at 5:07 PM Andrew Jones wrote: > > > > On Mon, Jan 13, 2025 at 04:36:34PM +0800, Yunhui Cui wrote: > > > Expose Zicbom through hwprobe and also provide a key to extract its > > > respective block size. > > > > > > Signed-off-by: Yunhui Cui > > > --- > > > Documentation/arch/riscv/hwprobe.rst | 6 ++++++ > > > arch/riscv/include/asm/hwprobe.h | 2 +- > > > arch/riscv/include/uapi/asm/hwprobe.h | 2 ++ > > > arch/riscv/kernel/sys_hwprobe.c | 6 ++++++ > > > 4 files changed, 15 insertions(+), 1 deletion(-) > > > > > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > > > index 955fbcd19ce9..7a47cbdbcf8e 100644 > > > --- a/Documentation/arch/riscv/hwprobe.rst > > > +++ b/Documentation/arch/riscv/hwprobe.rst > > > @@ -94,6 +94,9 @@ The following keys are defined: > > > * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as > > > ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. > > > > > > + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as > > > + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. > > > + > > > > This should come after RISCV_HWPROBE_EXT_SUPM since this document has the > > defines sorted in the order in which they are introduced (although I > > personally wouldn't mind if we ordered them alphabetically instead) > OK > > > > > > * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined > > > in version 1.0 of the Bit-Manipulation ISA extensions. > > > > > > @@ -273,6 +276,9 @@ The following keys are defined: > > > * :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which > > > represents the size of the Zicboz block in bytes. > > > > > > +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which > > > + represents the size of the Zicbom block in bytes. > > > + > > > > Should be moved below RISCV_HWPROBE_KEY_TIME_CSR_FREQ > > Why should it be moved below RISCV_HWPROBE_KEY_TIME_CSR_FREQ? Oh, right. It should be below RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF for the same reason as above (order of introduction). Thanks, drew