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Wed, 15 Jan 2025 09:49:53 -0800 (PST) Date: Wed, 15 Jan 2025 23:19:48 +0530 From: Manivannan Sadhasivam To: Andrew Lunn Cc: Anand Moon , Niklas Cassel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] PCI: dw-rockchip: Enable async probe by default Message-ID: <20250115174948.yippqwr5mekb6o4d@thinkpad> References: <5a3e8fda-f9e4-4c2f-847b-93f521b8313b@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Jan 07, 2025 at 02:13:34PM +0100, Andrew Lunn wrote: > > I was just trying to understand the call trace for mdio bus which got > > me confused. > > > > [0] https://lore.kernel.org/all/Z3fKkTSFFcU9gQLg@ryzen/ > > There is nothing particularly unusual in there. We see PCI bus > enumeration has found a device and bound a driver to it. The driver > has instantiated an MDIO bus, which has scanned the MDIO bus and found > a PHY. The phylib core then tried to load the kernel module needed to > drive the PHY. > > Just because it is a PCI device does not mean firmware has to control > all the hardware. Linux has no problems controlling all this, and it > saves reinventing the wheel in firmware, avoids firmware bugs, and > allows new features to be added etc. > Most of the time, it would be hard to define the properties of the PCI device's internal bus in devicetree. For instance, the pinctrl/clock properties which linux expects are to be connected to the host SoC, and not to the PCI device's SoC (unless the whole device's SoC is defined). Not saying that it is not possible but all, but very rare. - Mani -- மணிவண்ணன் சதாசிவம்