From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Patrick Rudolph <patrick.rudolph@9elements.com>,
Linus Walleij <linus.walleij@linaro.org>
Subject: [PATCH v1 07/16] pinctrl: cy8c95x0: Use better bitmap APIs where appropriate
Date: Fri, 17 Jan 2025 16:21:51 +0200 [thread overview]
Message-ID: <20250117142304.596106-8-andriy.shevchenko@linux.intel.com> (raw)
In-Reply-To: <20250117142304.596106-1-andriy.shevchenko@linux.intel.com>
There are bitmap_gather() and bitmap_scatter() that are factually
reimplemented in the driver. Use better bitmap APIs where appropriate.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/pinctrl/pinctrl-cy8c95x0.c | 33 +++++++++++-------------------
1 file changed, 12 insertions(+), 21 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c
index 970b6842b05b..d3f4e20d219f 100644
--- a/drivers/pinctrl/pinctrl-cy8c95x0.c
+++ b/drivers/pinctrl/pinctrl-cy8c95x0.c
@@ -137,7 +137,7 @@ static const struct dmi_system_id cy8c95x0_dmi_acpi_irq_info[] = {
* @irq_trig_low: I/O bits affected by a low voltage level
* @irq_trig_high: I/O bits affected by a high voltage level
* @push_pull: I/O bits configured as push pull driver
- * @shiftmask: Mask used to compensate for Gport2 width
+ * @map: Mask used to compensate for Gport2 width
* @nport: Number of Gports in this chip
* @gpio_chip: gpiolib chip
* @driver_data: private driver data
@@ -158,7 +158,7 @@ struct cy8c95x0_pinctrl {
DECLARE_BITMAP(irq_trig_low, MAX_LINE);
DECLARE_BITMAP(irq_trig_high, MAX_LINE);
DECLARE_BITMAP(push_pull, MAX_LINE);
- DECLARE_BITMAP(shiftmask, MAX_LINE);
+ DECLARE_BITMAP(map, MAX_LINE);
unsigned int nport;
struct gpio_chip gpio_chip;
unsigned long driver_data;
@@ -621,13 +621,8 @@ static int cy8c95x0_write_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
int ret;
/* Add the 4 bit gap of Gport2 */
- bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
- bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
- bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
-
- bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
- bitmap_shift_left(tval, tval, 4, MAX_LINE);
- bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
+ bitmap_scatter(tmask, mask, chip->map, MAX_LINE);
+ bitmap_scatter(tval, val, chip->map, MAX_LINE);
for (unsigned int i = 0; i < chip->nport; i++) {
/* Skip over unused banks */
@@ -652,19 +647,13 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
{
DECLARE_BITMAP(tmask, MAX_LINE);
DECLARE_BITMAP(tval, MAX_LINE);
- DECLARE_BITMAP(tmp, MAX_LINE);
int read_val;
u8 bits;
int ret;
/* Add the 4 bit gap of Gport2 */
- bitmap_andnot(tmask, mask, chip->shiftmask, MAX_LINE);
- bitmap_shift_left(tmask, tmask, 4, MAX_LINE);
- bitmap_replace(tmask, tmask, mask, chip->shiftmask, BANK_SZ * 3);
-
- bitmap_andnot(tval, val, chip->shiftmask, MAX_LINE);
- bitmap_shift_left(tval, tval, 4, MAX_LINE);
- bitmap_replace(tval, tval, val, chip->shiftmask, BANK_SZ * 3);
+ bitmap_scatter(tmask, mask, chip->map, MAX_LINE);
+ bitmap_scatter(tval, val, chip->map, MAX_LINE);
for (unsigned int i = 0; i < chip->nport; i++) {
/* Skip over unused banks */
@@ -684,8 +673,7 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg,
}
/* Fill the 4 bit gap of Gport2 */
- bitmap_shift_right(tmp, tval, 4, MAX_LINE);
- bitmap_replace(val, tmp, tval, chip->shiftmask, MAX_LINE);
+ bitmap_gather(tval, val, chip->map, MAX_LINE);
return 0;
}
@@ -1484,8 +1472,11 @@ static int cy8c95x0_probe(struct i2c_client *client)
return PTR_ERR(chip->regmap);
bitmap_zero(chip->push_pull, MAX_LINE);
- bitmap_zero(chip->shiftmask, MAX_LINE);
- bitmap_set(chip->shiftmask, 0, 20);
+
+ /* Setup HW pins mapping */
+ bitmap_fill(chip->map, MAX_LINE);
+ bitmap_clear(chip->map, 20, 4);
+
mutex_init(&chip->i2c_lock);
if (dmi_first_match(cy8c95x0_dmi_acpi_irq_info)) {
--
2.43.0.rc1.1336.g36b5255a03ac
next prev parent reply other threads:[~2025-01-17 14:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-17 14:21 [PATCH v1 00/16] pinctrl: cy8c95x0: Bugfixes and cleanups Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 01/16] pinctrl: cy8c95x0: Respect IRQ trigger settings from firmware Andy Shevchenko
2025-01-27 10:03 ` Linus Walleij
2025-02-03 12:13 ` Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 02/16] pinctrl: cy8c95x0: Rename PWMSEL to SELPWM Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 03/16] pinctrl: cy8c95x0: Enable regmap locking for debug Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 04/16] pinctrl: cy8c95x0: Fix off-by-one in the regmap range settings Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 05/16] pinctrl: cy8c95x0: Remove incorrectly set fields in regmap configuration Andy Shevchenko
2025-01-17 15:01 ` Patrick Rudolph
2025-01-17 15:13 ` Andy Shevchenko
2025-01-17 15:15 ` Andy Shevchenko
2025-01-17 16:47 ` Andy Shevchenko
2025-02-03 9:21 ` Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 06/16] pinctrl: cy8c95x0: Avoid accessing reserved registers Andy Shevchenko
2025-01-17 14:21 ` Andy Shevchenko [this message]
2025-01-17 14:21 ` [PATCH v1 08/16] pinctrl: cy8c95x0; Switch to use for_each_set_clump8() Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 09/16] pinctrl: cy8c95x0: Transform to cy8c95x0_regmap_read_bits() Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 10/16] pinctrl: cy8c95x0: Remove redundant check in cy8c95x0_regmap_update_bits_base() Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 11/16] pinctrl: cy8c95x0: Replace 'return ret' by 'return 0' in some cases Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 12/16] pinctrl: cy8c95x0: Initialise boolean variable with boolean values Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 13/16] pinctrl: cy8c95x0: Get rid of cy8c95x0_pinmux_direction() forward declaration Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 14/16] pinctrl: cy8c95x0: Drop unneeded casting Andy Shevchenko
2025-01-17 14:21 ` [PATCH v1 15/16] pinctrl: cy8c95x0: Separate EEPROM related register definitios Andy Shevchenko
2025-01-17 14:22 ` [PATCH v1 16/16] pinctrl: cy8c95x0: Fix comment style Andy Shevchenko
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