From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A18D6211712 for ; Wed, 22 Jan 2025 14:58:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737557918; cv=none; b=MsjDT479XINSvWRA95dZXmbA8sF5omgxcQzLKqpSJ304dhBSQthAAv9aanwmIQmcCXhp1h4pNzvdd6GM7/k3M2q/OGrRJEvQEwLiyEaZM8D2+fGFs6ifBB7Tly5o1uB7m1nMAan6ThkImoRSgz31PBlazcmqBWTN1oUYPFdVqII= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1737557918; c=relaxed/simple; bh=ljGq6f8Xeef0wHQesbpb2GW5jePoYUwea799goqERzs=; h=Date:From:To:CC:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=c7ntLV2DBp+BPtR6Gfoxuh+if6D7ra5t01pZi9ZjflXIGOo1xZl6NiAHHc87zSuiqcrzfBglx3h7BzT1i2D6sbBi+MwLwBdZz3ig8d0/tOdvnOrz7reTstZTvUL4tDCD5koYXV7IsLa425fDzFIdM3Str/+LKk4LwvnJgttZXQ0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=khZ26zZx; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="khZ26zZx" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 50MEwMPa1008063 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 22 Jan 2025 08:58:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1737557902; bh=Njmu/kDM1xSU/K64/+IR5Y3ODQTNZCGbM8fmRUrXiFQ=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=khZ26zZxSHNvE4D7g4EhGnJbVj2h1OdbuQBIWEuXPq2D73BcoSv7XwxllUNoSC35P zpxoEb6mkyTPibDVDCL4o+0+hcqtYxwJuZb2mhMnKaMwRtN9xq6KCfADMKWL3mraKO AcqEbjs0w6AvVvyUR15RXF6wMlkt9kI5HsYXS3Ks= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 50MEwMZ8102967 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 22 Jan 2025 08:58:22 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 22 Jan 2025 08:58:21 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 22 Jan 2025 08:58:22 -0600 Received: from localhost (uda0133052.dhcp.ti.com [128.247.81.232]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 50MEwM4U030645; Wed, 22 Jan 2025 08:58:22 -0600 Date: Wed, 22 Jan 2025 08:58:22 -0600 From: Nishanth Menon To: Daniel Schultz CC: Andrew Halaney , Catalin Marinas , Will Deacon , Siddharth Vadapalli , "vigneshr@ti.com" , "srk@ti.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] arm64: defconfig: Enable PCI_J721E Message-ID: <20250122145822.4ewsmkk6ztbeejzf@slashing> References: <20240807-pci-j721e-defconfig-v1-1-b97e5f4564f6@redhat.com> <8b700897-1653-49f2-8fba-e5fce13a5447@phytec.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <8b700897-1653-49f2-8fba-e5fce13a5447@phytec.de> X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 14:53-20250122, Daniel Schultz wrote: > can someone please apply this patch? It's actually required by all TI > AM6 devices with PCIe, e.g. AM64x. > > - Daniel > > On 07.08.24 22:15, Andrew Halaney wrote: > > Enable PCI_J721E for usage in both host and endpoint modes. > > This is used by boards such as Texas Instrument's SK-AM69 and > > J784S4XEVM. > > > > Signed-off-by: Andrew Halaney > Tested-By: Daniel Schultz > > --- > > arch/arm64/configs/defconfig | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > > index 01dd286ba7ef0..e5222dbedd387 100644 > > --- a/arch/arm64/configs/defconfig > > +++ b/arch/arm64/configs/defconfig > > @@ -225,6 +225,8 @@ CONFIG_PCIE_RCAR_HOST=y > > CONFIG_PCIE_RCAR_EP=y > > CONFIG_PCIE_ROCKCHIP_HOST=m > > CONFIG_PCI_XGENE=y > > +CONFIG_PCI_J721E_HOST=y > > +CONFIG_PCI_J721E_EP=y > > CONFIG_PCI_IMX6_HOST=y > > CONFIG_PCI_LAYERSCAPE=y > > CONFIG_PCI_HISI=y please make them as modules. no point in growing the default Image file. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D