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Mon, 03 Feb 2025 07:20:57 -0800 (PST) Date: Mon, 3 Feb 2025 20:50:52 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio Subject: Re: [PATCH v4 3/4] PCI: dwc: Improve handling of PCIe lane configuration Message-ID: <20250203152052.kwbmt6bhjzv55ddk@thinkpad> References: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> <20250124-preset_v2-v4-3-0b512cad08e1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250124-preset_v2-v4-3-0b512cad08e1@oss.qualcomm.com> On Fri, Jan 24, 2025 at 04:52:49PM +0530, Krishna Chaitanya Chundru wrote: > Currently even if the number of lanes hardware supports is equal to > the number lanes provided in the devicetree, the driver is trying to > configure again the maximum number of lanes which is not needed. > > Update number of lanes only when it is not equal to hardware capability. > > And also if the num-lanes property is not present in the devicetree > update the num_lanes with the maximum hardware supports. > > Introduce dw_pcie_link_get_max_link_width() to get the maximum lane > width the hardware supports. > > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ > drivers/pci/controller/dwc/pcie-designware.c | 14 +++++++++++++- > drivers/pci/controller/dwc/pcie-designware.h | 1 + > 3 files changed, 17 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 3e41865c7290..2cd0acbf9e18 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > > dw_pcie_iatu_detect(pci); > > + if (pci->num_lanes < 1) > + pci->num_lanes = dw_pcie_link_get_max_link_width(pci); > + > /* > * Allocate the resource for MSG TLP before programming the iATU > * outbound window in dw_pcie_setup_rc(). Since the allocation depends > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 6d6cbc8b5b2c..acb2a963ae1a 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -736,6 +736,16 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) > > } > > +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) > +{ > + u32 lnkcap; > + u8 cap; > + > + cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + lnkcap = dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); > + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); > +} > + > static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_lanes) > { > u32 lnkcap, lwsc, plc; > @@ -1069,6 +1079,7 @@ void dw_pcie_edma_remove(struct dw_pcie *pci) > > void dw_pcie_setup(struct dw_pcie *pci) > { > + int num_lanes = dw_pcie_link_get_max_link_width(pci); > u32 val; > > dw_pcie_link_set_max_speed(pci); > @@ -1102,5 +1113,6 @@ void dw_pcie_setup(struct dw_pcie *pci) > val |= PORT_LINK_DLL_LINK_EN; > dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); > > - dw_pcie_link_set_max_link_width(pci, pci->num_lanes); > + if (num_lanes != pci->num_lanes) Move this check inside dw_pcie_link_set_max_link_width() where we are already checking for !num_lanes. - Mani -- மணிவண்ணன் சதாசிவம்