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Mon, 03 Feb 2025 08:16:01 -0800 (PST) Date: Mon, 3 Feb 2025 21:45:55 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, konrad.dybcio@oss.qualcomm.com, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Bjorn Andersson , Konrad Dybcio Subject: Re: [PATCH v4 4/4] PCI: dwc: Add support for configuring lane equalization presets Message-ID: <20250203161555.a32gpzv4j6cjajs5@thinkpad> References: <20250124-preset_v2-v4-0-0b512cad08e1@oss.qualcomm.com> <20250124-preset_v2-v4-4-0b512cad08e1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250124-preset_v2-v4-4-0b512cad08e1@oss.qualcomm.com> On Fri, Jan 24, 2025 at 04:52:50PM +0530, Krishna Chaitanya Chundru wrote: > PCIe equalization presets are predefined settings used to optimize > signal integrity by compensating for signal loss and distortion in > high-speed data transmission. > > Based upon the number of lanes and the data rate supported, write > the preset data read from the device tree in to the lane equalization > control registers. > > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 41 +++++++++++++++++++++++ > drivers/pci/controller/dwc/pcie-designware.h | 3 ++ > include/uapi/linux/pci_regs.h | 3 ++ > 3 files changed, 47 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 2cd0acbf9e18..eced862fb8dd 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > if (pci->num_lanes < 1) > pci->num_lanes = dw_pcie_link_get_max_link_width(pci); > > + ret = of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes); > + if (ret) > + goto err_free_msi; > + > /* > * Allocate the resource for MSG TLP before programming the iATU > * outbound window in dw_pcie_setup_rc(). Since the allocation depends > @@ -802,6 +806,42 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > return 0; > } > > +static void dw_pcie_program_presets(struct dw_pcie *pci, u8 cap_id, u8 lane_eq_offset, > + u8 lane_reg_size, u8 *presets, u8 num_lanes) > +{ > + u32 cap; > + int i; > + > + cap = dw_pcie_find_ext_capability(pci, cap_id); > + if (!cap) > + return; > + > + /* > + * Write preset values to the registers byte-by-byte for the given > + * number of lanes and register size. > + */ > + for (i = 0; i < num_lanes * lane_reg_size; i++) > + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); So this essentially means that the presets value derived from DT should be equal to 'num_lanes', otherwise this function will write 0 for the undefined lanes. But this should be taken care by binding as I mentioned in my review and code should not worry about it. > +} > + > +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed]; > + > + /* For data rate of 8 GT/S each lane equalization control is 16bits wide */ > + if (speed >= PCIE_SPEED_8_0GT && pp->presets.eq_presets_8gts[0] != 0xff) > + dw_pcie_program_presets(pci, PCI_EXT_CAP_ID_SECPCI, PCI_SECPCI_LE_CTRL, > + 0x2, (u8 *)pp->presets.eq_presets_8gts, pci->num_lanes); You should just pass PCIE_SPEED_8_0GT to the dw_pcie_program_presets() helper and it should figure out the register bits, size and lane count inside. Like, dw_pcie_program_presets(pci, PCIE_SPEED_8_0GT); > + > + /* For data rate of 16 GT/S each lane equalization control is 8bits wide */ > + if (speed >= PCIE_SPEED_16_0GT && > + pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS][0] != 0xff) > + dw_pcie_program_presets(pci, PCI_EXT_CAP_ID_PL_16GT, PCI_PL_16GT_LE_CTRL, > + 0x1, pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS], > + pci->num_lanes); Same here. - Mani -- மணிவண்ணன் சதாசிவம்