From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D7F6122D4DA; Wed, 5 Feb 2025 10:50:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738752607; cv=none; b=QWZ0fX/N1KMAmZ7/IqgHzX3KmesfrKzBa48LXhXYU864o91NkuqhsAEl+fGkXrMNaIJ3eqHXA9i5UuAnIstORim/aJR6KobBZsRdNVn5M+2DUhJfm1Hdv20dRC/1mMgk3pvn8JuX85lp5wRsVy+wJgmxZ+u93kZQg6/iv3GIn98= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738752607; c=relaxed/simple; bh=KQOTWzbhGWsR9+/X0VDEcivnX/oxVCYyQt/frcwp37k=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PH/DGCARxCxI9PO56rBZtjO+nLZVpePvZMbOvmrZVHa1reyUkHVkZ71EdvYBjWvn7mJqmUbwUUl16uCUgetHXX4+3TELhvO4lreRRZ35lWFk94KMO3hxyId6QUZQLBPFYjlev7VRY+xhvN4AGOSw6tCmAn76GUr4Rzm+E6lFZ7k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu; spf=pass smtp.mailfrom=prolan.hu; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b=YPaTCIhd; arc=none smtp.client-ip=193.68.50.107 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=prolan.hu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=prolan.hu Authentication-Results: smtp.subspace.kernel.org; dkim=pass (4096-bit key) header.d=prolan.hu header.i=@prolan.hu header.b="YPaTCIhd" Received: from proxmox-mailgw.intranet.prolan.hu (localhost.localdomain [127.0.0.1]) by proxmox-mailgw.intranet.prolan.hu (Proxmox) with ESMTP id ADD9BA037B; Wed, 5 Feb 2025 11:50:02 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:in-reply-to:message-id:mime-version:references :reply-to:subject:subject:to:to; s=mail; bh=spcugB6t6p78x878lmlq UL8jciWNu5Mk1BUINRx7Dfc=; b=YPaTCIhdnLydCfO6rCc/SmKW7gJAUJ3DinjO XLgsi3pfr6P0N+3lnghvktG7yuuu1ESnlf6JPFRhEPTt8BFmTM5E99W0I+s51cPP xScZsc8XRfrKvXkvWtky1+O6eBGkzRwZ73LV8Goj5Wsgi3SMY5JlLS7etHMsU0yV KpCpgGDYwqANtYm4O2QNMvpnyNmcDKlMEH+2MM2UlqbYuXjFK6B2kPHAZDTNq+Tr g5nVBxpuU9hd3cFFy3bVfyytIyMje8YAG5UQDV/IAqV0kTia2kBOvj7HLj7PfoEG G3udsarQqxMIxN/+dSf+4Fjhpl/FDVFTseIgmnwXukSG5KBEhNY4frlSzPBKeGXY h83VIkX/qAPKhQDdIT/1J0iAcBQ8ejQ/5OSXAMrymrmuqH9r5fBoF0vccCIJPBdx lCMKlJMfcgsiiz0tJ3KGgnhzQp0+bCP47IyxTJ0C5O/C5dk+T+UhHvQf+OZcjmiL 2AUDNLo0l4s5CH07GXtqxf0n0MRz8hTKrnzrXq7Wl8LiUs2A//t3xMHsm+SyJjBa TdwQOaAxPekWXnchNPyz5L/CPfg8eWn6MnkIH8unDDeKuG8uPsOknwn6rAUMN5OE UGUitADqQW/PoL3lAze65x7/6D49Rk5egcdbywyMxYBllj7lwTM4RoushY8nbvL1 5Z1hEqo= From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= To: , , CC: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= , "Kamel Bouhara" , William Breathitt Gray Subject: [PATCH v3 1/2] counter: microchip-tcb-capture: Add IRQ handling Date: Wed, 5 Feb 2025 11:49:53 +0100 Message-ID: <20250205104957.95236-2-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250205104957.95236-1-csokas.bence@prolan.hu> References: <20250205104957.95236-1-csokas.bence@prolan.hu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1738752601;VERSION=7985;MC=1293086803;ID=233956;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A29ACD94852667264 Add interrupt servicing to allow userspace to wait for the following events: * Change-of-state caused by external trigger * Capture of timer value into RA/RB * Compare to RC register * Overflow Signed-off-by: Bence Csókás --- Notes: New in v2 Changes in v3: * Add IRQs for Capture events (from next patch) * Add IRQ for RC Compare * Add events as bullet points to commit msg drivers/counter/microchip-tcb-capture.c | 67 +++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c index 2f096a5b973d..fef4bb69b486 100644 --- a/drivers/counter/microchip-tcb-capture.c +++ b/drivers/counter/microchip-tcb-capture.c @@ -6,10 +6,12 @@ */ #include #include +#include #include #include #include #include +#include #include #include #include @@ -18,6 +20,9 @@ ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \ ATMEL_TC_LDBSTOP) +#define ATMEL_TC_DEF_IRQS (ATMEL_TC_ETRGS | ATMEL_TC_COVFS | \ + ATMEL_TC_LDRAS | ATMEL_TC_LDRBS | ATMEL_TC_CPCS) + #define ATMEL_TC_QDEN BIT(8) #define ATMEL_TC_POSEN BIT(9) @@ -27,6 +32,7 @@ struct mchp_tc_data { int qdec_mode; int num_channels; int channel[2]; + int irq; }; static const enum counter_function mchp_tc_count_functions[] = { @@ -294,6 +300,60 @@ static const struct of_device_id atmel_tc_of_match[] = { { /* sentinel */ } }; +static irqreturn_t mchp_tc_isr(int irq, void *dev_id) +{ + struct counter_device *const counter = dev_id; + struct mchp_tc_data *const priv = counter_priv(counter); + u32 sr, mask; + + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr); + regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], IMR), &mask); + + sr &= mask; + if (!(sr & ATMEL_TC_ALL_IRQ)) + return IRQ_NONE; + + if (sr & ATMEL_TC_ETRGS) + counter_push_event(counter, COUNTER_EVENT_CHANGE_OF_STATE, 0); + if (sr & ATMEL_TC_LDRAS) + counter_push_event(counter, COUNTER_EVENT_CAPTURE, 0); + if (sr & ATMEL_TC_LDRBS) + counter_push_event(counter, COUNTER_EVENT_CAPTURE, 1); + if (sr & ATMEL_TC_CPCS) + counter_push_event(counter, COUNTER_EVENT_THRESHOLD, 2); + if (sr & ATMEL_TC_COVFS) + counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0); + + return IRQ_HANDLED; +} + +static void mchp_tc_irq_remove(void *ptr) +{ + struct mchp_tc_data *priv = ptr; + + regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IDR), ATMEL_TC_DEF_IRQS); +} + +static int mchp_tc_irq_enable(struct counter_device *const counter) +{ + struct mchp_tc_data *const priv = counter_priv(counter); + int ret = devm_request_irq(counter->parent, priv->irq, mchp_tc_isr, 0, + dev_name(counter->parent), counter); + + if (ret < 0) + return ret; + + ret = regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], IER), ATMEL_TC_DEF_IRQS); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(counter->parent, mchp_tc_irq_remove, priv); + if (ret < 0) + return ret; + + return 0; +} + static void mchp_tc_clk_remove(void *ptr) { clk_disable_unprepare((struct clk *)ptr); @@ -378,6 +438,13 @@ static int mchp_tc_probe(struct platform_device *pdev) counter->num_signals = ARRAY_SIZE(mchp_tc_count_signals); counter->signals = mchp_tc_count_signals; + priv->irq = of_irq_get(np->parent, 0); + if (priv->irq > 0) { + ret = mchp_tc_irq_enable(counter); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to set up IRQ"); + } + ret = devm_counter_add(&pdev->dev, counter); if (ret < 0) return dev_err_probe(&pdev->dev, ret, "Failed to add counter\n"); -- 2.48.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fw2.prolan.hu (fw2.prolan.hu [193.68.50.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85FD421A43C; Wed, 5 Feb 2025 10:51:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.68.50.107 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738752702; cv=none; b=F3e1MYQYpUUFYuzQqQPOpimu90ORi5YwQptWZB3/aeHISNJK7dDL+DFLXaR+JRAqO3HWyeBS0+Wkoe/9Vp/YLDaJTgvzcIJcdic/ZBk20Wv2pchOXlPeWnLRZ6qg2S+M0WN606mWcfEufvkOw6d4CqirZWn8xsFup4Kw3vZUwHI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 5 Feb 2025 11:51:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=prolan.hu; h=cc :cc:content-transfer-encoding:content-type:content-type:date :from:from:message-id:mime-version:reply-to:subject:subject:to :to; s=mail; bh=A8a8Vknd+Ac1B5NbwMCS9Rp6ox5pHlVEJ+QCEfo6ioE=; b= WnoYpEILKm9SvCt3yFSNGC/pL8zToIpwkbYHyPlxp+VVP2rAtXJYcxeEbw4g1E4R X14ODohHKGFOHhtxnIaAU6klhR1GAc9GZK4rOXVZFEcsBjcc6QIqIAwggrhwKZCf TzahDJATPmmkcZ0HC4vhLitYFpjoq6pwHZJkpvz/QFlOjFfikS5p2oFVnRZ/g72s 4c7KZXhD232EbMksPdbERtFGUNeevdlhX89lSpPzcnf+u0M6JoZXIQ8JpKD5lxrx Tz6OBDNpbotA+Je4hevaZ+Chiy80I+LU9Qcry4CYD5/CTfjytbTVaNGeRKZPhVtK huFPGYvVQfS+giv5dcy3vkE48KgdtOnzBPhZ8eUMGf3ZxFPcBpx9Vgyche2h/644 rhsuDfUgN4LZFMg60ZFipKmy6+2P8AHJz7UJynvvIG7o7EMNiycwH+bXO7hTd1Fq GoOWxojUrpCb1dPMeGTJ4oBBIOfhsjAgkUUG1tDDupW2K8I7Zhl60VU8GlTg3kth H92Sfa/GXZFSqchZwH8Kfw/789l5TMZmbOpKeeHux3AqFBEJh9GZn/hf8dn5S8Dg +h9yLrpGiqvLeIOLZ7gOmlVyc/mv7YWrWwyYut2K3Nkmr8+hw627AlA5y0PpYwsQ xd6+28uXypSWwG31J7PypaUvdvLSrDGwUn8jvF7VFzg= From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= To: , , CC: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= , "Kamel Bouhara" , William Breathitt Gray Subject: [PATCH v3 0/2] microchip-tcb-capture: Add Capture, Compare, Overflow etc. events Date: Wed, 5 Feb 2025 11:50:43 +0100 Message-ID: <20250205104957.95236-2-csokas.bence@prolan.hu> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-ESET-AS: R=OK;S=0;OP=CALC;TIME=1738752695;VERSION=7984;MC=1779217303;ID=244308;TRN=0;CRV=0;IPC=;SP=0;SIPS=0;PI=3;F=0 X-ESET-Antispam: OK X-EsetResult: clean, is OK X-EsetId: 37303A2980D94852667264 Message-ID: <20250205105043.GZ2GiOuZ93zyLzEs81RUQlV0ncWGq4g6kvV4fhv3hU4@z> The TCB has three R/W-able "general purpose" hardware registers: RA, RB and RC. The hardware is capable of: * sampling Counter Value Register (CV) to RA/RB on a trigger edge * sending an interrupt of this change * sending an interrupt on CV change due to trigger * triggering an interrupt on CV compare to RC * stop counting after sampling to RB To enable using these features in user-space, an interrupt handler was added, generating the necessary counter events. On top, RA/B/C registers are added as Count Extensions. Bence Csókás (2): counter: microchip-tcb-capture: Add IRQ handling counter: microchip-tcb-capture: Add capture extensions for registers RA-RC drivers/counter/microchip-tcb-capture.c | 125 ++++++++++++++++++++++++ 1 file changed, 125 insertions(+) -- 2.48.1