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Wed, 12 Feb 2025 09:23:15 -0800 (PST) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 41be03b00d2f7-ad54f1691ddsm6001705a12.61.2025.02.12.09.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Feb 2025 09:23:14 -0800 (PST) From: Nick Chan Date: Thu, 13 Feb 2025 01:22:28 +0800 Subject: [PATCH v2 05/10] drivers/perf: apple_m1: Support per-implementation PMU start Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250213-apple-cpmu-v2-5-87b361932e88@gmail.com> References: <20250213-apple-cpmu-v2-0-87b361932e88@gmail.com> In-Reply-To: <20250213-apple-cpmu-v2-0-87b361932e88@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support for implementations that deliver its interrupts in ways other than FIQ will be added, which requires a per-implementation start function. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index e7b898aef45e9e18899693774ad673fd370b19d7..12eba1075b36768afc29e211926331b9a426c54f 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -605,7 +605,6 @@ static int apple_pmu_init_common(struct arm_pmu *cpu_pmu, u32 counters) cpu_pmu->read_counter = m1_pmu_read_counter; cpu_pmu->write_counter = m1_pmu_write_counter; cpu_pmu->clear_event_idx = m1_pmu_clear_event_idx; - cpu_pmu->start = m1_pmu_start; cpu_pmu->stop = m1_pmu_stop; cpu_pmu->set_event_filter = m1_pmu_set_event_filter; @@ -622,6 +621,7 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m1_pmu_map_event; cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; return apple_pmu_init_common(cpu_pmu, M1_PMU_NR_COUNTERS); } @@ -631,6 +631,7 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m1_pmu_map_event; cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; return apple_pmu_init_common(cpu_pmu, M1_PMU_NR_COUNTERS); } @@ -640,6 +641,7 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m2_pmu_map_event; cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; return apple_pmu_init_common(cpu_pmu, M1_PMU_NR_COUNTERS); } @@ -649,6 +651,7 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->get_event_idx = m1_pmu_get_event_idx; cpu_pmu->map_event = m2_pmu_map_event; cpu_pmu->reset = m1_pmu_reset; + cpu_pmu->start = m1_pmu_start; return apple_pmu_init_common(cpu_pmu, M1_PMU_NR_COUNTERS); } -- 2.48.1