Re: [PATCH v2 6/7] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support

[kernel test robot <lkp@intel.com>]

Hi Fabrizio,

kernel test robot noticed the following build warnings:

[auto build test WARNING on vkoul-dmaengine/next]
[also build test WARNING on geert-renesas-drivers/renesas-clk robh/for-next linus/master v6.14-rc2 next-20250213]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Fabrizio-Castro/clk-renesas-r9a09g057-Add-entries-for-the-DMACs/20250213-061714
base:   https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git next
patch link:    https://lore.kernel.org/r/20250212221305.431716-7-fabrizio.castro.jz%40renesas.com
patch subject: [PATCH v2 6/7] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support
config: powerpc64-randconfig-001-20250213 (https://download.01.org/0day-ci/archive/20250213/202502132123.1ePmN98r-lkp@intel.com/config)
compiler: clang version 19.1.3 (https://github.com/llvm/llvm-project ab51eccf88f5321e7c60591c5546b254b6afab99)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250213/202502132123.1ePmN98r-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502132123.1ePmN98r-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/dma/sh/rz-dmac.c:979:15: warning: cast to smaller integer type 'enum rz_dmac_type' from 'const void *' [-Wvoid-pointer-to-enum-cast]
     979 |         dmac->type = (enum rz_dmac_type)of_device_get_match_data(dmac->dev);
         |                      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   1 warning generated.


vim +979 drivers/dma/sh/rz-dmac.c

   962	
   963	static int rz_dmac_probe(struct platform_device *pdev)
   964	{
   965		const char *irqname = "error";
   966		struct dma_device *engine;
   967		struct rz_dmac *dmac;
   968		int channel_num;
   969		int ret;
   970		int irq;
   971		u8 i;
   972	
   973		dmac = devm_kzalloc(&pdev->dev, sizeof(*dmac), GFP_KERNEL);
   974		if (!dmac)
   975			return -ENOMEM;
   976	
   977		dmac->dev = &pdev->dev;
   978		platform_set_drvdata(pdev, dmac);
 > 979		dmac->type = (enum rz_dmac_type)of_device_get_match_data(dmac->dev);
   980	
   981		ret = rz_dmac_parse_of(&pdev->dev, dmac);
   982		if (ret < 0)
   983			return ret;
   984	
   985		dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
   986					      sizeof(*dmac->channels), GFP_KERNEL);
   987		if (!dmac->channels)
   988			return -ENOMEM;
   989	
   990		/* Request resources */
   991		dmac->base = devm_platform_ioremap_resource(pdev, 0);
   992		if (IS_ERR(dmac->base))
   993			return PTR_ERR(dmac->base);
   994	
   995		if (dmac->type == RZ_DMAC_RZG2L) {
   996			dmac->ext_base = devm_platform_ioremap_resource(pdev, 1);
   997			if (IS_ERR(dmac->ext_base))
   998				return PTR_ERR(dmac->ext_base);
   999		} else {
  1000			ret = rz_dmac_parse_of_icu(&pdev->dev, dmac);
  1001			if (ret)
  1002				return ret;
  1003		}
  1004	
  1005		/* Register interrupt handler for error */
  1006		irq = platform_get_irq_byname(pdev, irqname);
  1007		if (irq < 0)
  1008			return irq;
  1009	
  1010		ret = devm_request_irq(&pdev->dev, irq, rz_dmac_irq_handler, 0,
  1011				       irqname, NULL);
  1012		if (ret) {
  1013			dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n",
  1014				irq, ret);
  1015			return ret;
  1016		}
  1017	
  1018		/* Initialize the channels. */
  1019		INIT_LIST_HEAD(&dmac->engine.channels);
  1020	
  1021		dmac->rstc = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
  1022		if (IS_ERR(dmac->rstc))
  1023			return dev_err_probe(&pdev->dev, PTR_ERR(dmac->rstc),
  1024					     "failed to get resets\n");
  1025	
  1026		pm_runtime_enable(&pdev->dev);
  1027		ret = pm_runtime_resume_and_get(&pdev->dev);
  1028		if (ret < 0) {
  1029			dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n");
  1030			goto err_pm_disable;
  1031		}
  1032	
  1033		ret = reset_control_deassert(dmac->rstc);
  1034		if (ret)
  1035			goto err_pm_runtime_put;
  1036	
  1037		for (i = 0; i < dmac->n_channels; i++) {
  1038			ret = rz_dmac_chan_probe(dmac, &dmac->channels[i], i);
  1039			if (ret < 0)
  1040				goto err;
  1041		}
  1042	
  1043		/* Register the DMAC as a DMA provider for DT. */
  1044		ret = of_dma_controller_register(pdev->dev.of_node, rz_dmac_of_xlate,
  1045						 NULL);
  1046		if (ret < 0)
  1047			goto err;
  1048	
  1049		/* Register the DMA engine device. */
  1050		engine = &dmac->engine;
  1051		dma_cap_set(DMA_SLAVE, engine->cap_mask);
  1052		dma_cap_set(DMA_MEMCPY, engine->cap_mask);
  1053		rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL);
  1054		rz_dmac_writel(dmac, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL);
  1055	
  1056		engine->dev = &pdev->dev;
  1057	
  1058		engine->device_alloc_chan_resources = rz_dmac_alloc_chan_resources;
  1059		engine->device_free_chan_resources = rz_dmac_free_chan_resources;
  1060		engine->device_tx_status = dma_cookie_status;
  1061		engine->device_prep_slave_sg = rz_dmac_prep_slave_sg;
  1062		engine->device_prep_dma_memcpy = rz_dmac_prep_dma_memcpy;
  1063		engine->device_config = rz_dmac_config;
  1064		engine->device_terminate_all = rz_dmac_terminate_all;
  1065		engine->device_issue_pending = rz_dmac_issue_pending;
  1066		engine->device_synchronize = rz_dmac_device_synchronize;
  1067	
  1068		engine->copy_align = DMAENGINE_ALIGN_1_BYTE;
  1069		dma_set_max_seg_size(engine->dev, U32_MAX);
  1070	
  1071		ret = dma_async_device_register(engine);
  1072		if (ret < 0) {
  1073			dev_err(&pdev->dev, "unable to register\n");
  1074			goto dma_register_err;
  1075		}
  1076		return 0;
  1077	
  1078	dma_register_err:
  1079		of_dma_controller_free(pdev->dev.of_node);
  1080	err:
  1081		channel_num = i ? i - 1 : 0;
  1082		for (i = 0; i < channel_num; i++) {
  1083			struct rz_dmac_chan *channel = &dmac->channels[i];
  1084	
  1085			dma_free_coherent(&pdev->dev,
  1086					  sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC,
  1087					  channel->lmdesc.base,
  1088					  channel->lmdesc.base_dma);
  1089		}
  1090	
  1091		reset_control_assert(dmac->rstc);
  1092	err_pm_runtime_put:
  1093		pm_runtime_put(&pdev->dev);
  1094	err_pm_disable:
  1095		pm_runtime_disable(&pdev->dev);
  1096	
  1097		return ret;
  1098	}
  1099	

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