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Fri, 14 Feb 2025 06:30:28 -0800 (PST) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-220d545c8d1sm29490315ad.113.2025.02.14.06.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Feb 2025 06:30:28 -0800 (PST) From: Nick Chan Subject: [PATCH v4 00/11] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support Date: Fri, 14 Feb 2025 22:28:26 +0800 Message-Id: <20250214-apple-cpmu-v4-0-ffca0e45147e@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAApTr2cC/3XM3QrCIBjG8VsZHmdM3625jrqP6MDp6ybsQ7SkG Lv33CBYQYfPA7//TAJ6i4Gcs5l4jDbYaUyjOGREdXJskVqdNuE5L3POGJXO9UiVGx60lKUELaE uBJAEnEdjn1vseku7s+E++dfWjmx9Pxm+z0RGc2qEqgyXilUFXNpB2v6opoGsmcj3FL4oT1RUD ZxYDRyF+KXwn0KiDVZGSI1aMLOny7K8AfzAuRoaAQAA X-Change-ID: 20250211-apple-cpmu-5a5a3da39483 To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 This series adds support for the CPU PMU in the older Apple A7-A11, T2 SoCs. These PMUs may have a different event layout, less counters, or deliver their interrupts via IRQ instead of a FIQ. Since some of those older SoCs support 32-bit EL0, counting for 32-bit EL0 also need to be enabled by the driver where applicable. Patch 1 adds the DT bindings. Patch 2-6 prepares the driver to allow adding support for those older SoCs. Patch 7-11 adds support for the older SoCs. Signed-off-by: Nick Chan --- Changes in v4: - Support per-implementation event attr group - Fix Apple A7 event attr groups - Link to v3: https://lore.kernel.org/r/20250213-apple-cpmu-v3-0-be7f8aded81f@gmail.com Changes in v3: - Configure PMC8 and PMC9 for 32-bit EL0 - Remove redundant _common suffix from shared functions - Link to v2: https://lore.kernel.org/r/20250213-apple-cpmu-v2-0-87b361932e88@gmail.com Changes in v2: - Remove unused flags parameter from apple_pmu_init_common() - Link to v1: https://lore.kernel.org/r/20250212-apple-cpmu-v1-0-f8c7f2ac1743@gmail.com --- Nick Chan (11): dt-bindings: arm: pmu: Add Apple A7-A11 SoC CPU PMU compatibles drivers/perf: apple_m1: Support per-implementation event tables drivers/perf: apple_m1: Support a per-implementation number of counters drivers/perf: apple_m1: Support configuring counters for 32-bit EL0 drivers/perf: apple_m1: Support per-implementation PMU startup drivers/perf: apple_m1: Support per-implementation event attr group drivers/perf: apple_m1: Add Apple A7 support drivers/perf: apple_m1: Add Apple A8/A8X support drivers/perf: apple_m1: Add A9/A9X support drivers/perf: apple_m1: Add Apple A10/A10X/T2 Support drivers/perf: apple_m1: Add Apple A11 Support Documentation/devicetree/bindings/arm/pmu.yaml | 6 + arch/arm64/include/asm/apple_m1_pmu.h | 3 + drivers/perf/apple_m1_cpu_pmu.c | 801 ++++++++++++++++++++++++- 3 files changed, 777 insertions(+), 33 deletions(-) --- base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b change-id: 20250211-apple-cpmu-5a5a3da39483 Best regards, -- Nick Chan