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Fri, 14 Feb 2025 00:44:34 -0800 (PST) Date: Fri, 14 Feb 2025 14:14:27 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com Subject: Re: [PATCH v6 1/4] arm64: dts: qcom: x1e80100: Add PCIe lane equalization preset properties Message-ID: <20250214084427.5ciy5ks6oypr3dvg@thinkpad> References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> <20250210-preset_v6-v6-1-cbd837d0028d@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250210-preset_v6-v6-1-cbd837d0028d@oss.qualcomm.com> On Mon, Feb 10, 2025 at 01:00:00PM +0530, Krishna Chaitanya Chundru wrote: > Add PCIe lane equalization preset properties for 8 GT/s and 16 GT/s data > rates used in lane equalization procedure. > > Signed-off-by: Krishna Chaitanya Chundru > --- > This patch depends on the this dt binding pull request which got recently > merged: https://github.com/devicetree-org/dt-schema/pull/146 > --- > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 4936fa5b98ff..1b815d4eed5c 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > phys = <&pcie3_phy>; > phy-names = "pciephy"; > > + eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, > + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; Why 2 16bit arrays? - Mani -- மணிவண்ணன் சதாசிவம்