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Fri, 14 Feb 2025 05:18:46 -0800 (PST) Date: Fri, 14 Feb 2025 18:48:40 +0530 From: Manivannan Sadhasivam To: Komal Bajaj Cc: bp@alien8.de, tony.luck@intel.com, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, andy.gross@linaro.org, vnkgutta@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] qcom: llcc/edac: Correct interrupt enable register configuration Message-ID: <20250214131840.desyshjr3dbb5lyl@thinkpad> References: <20241119064608.12326-1-quic_kbajaj@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241119064608.12326-1-quic_kbajaj@quicinc.com> On Tue, Nov 19, 2024 at 12:16:08PM +0530, Komal Bajaj wrote: > The previous implementation incorrectly configured the cmn_interrupt_2_enable > register for interrupt handling. Using cmn_interrupt_2_enable to configure Tag, > Data RAM ECC interrupts would lead to issues like double handling of the > interrupts (EL1 and EL3) as cmn_interrupt_2_enable is meant to be configured > for interrupts which needs to be handled by EL3. > > EL1 LLCC EDAC driver needs to use cmn_interrupt_0_enable register to > configure Tag, Data RAM ECC interrupts instead of cmn_interrupt_2_enable. > Cc: stable@vger.kernel.org > Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") > Signed-off-by: Komal Bajaj Reviewed-by: Manivannan Sadhasivam - Mani > --- > drivers/edac/qcom_edac.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c > index a9a8ba067007..0fd7a777fe7d 100644 > --- a/drivers/edac/qcom_edac.c > +++ b/drivers/edac/qcom_edac.c > @@ -95,7 +95,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b > * Configure interrupt enable registers such that Tag, Data RAM related > * interrupts are propagated to interrupt controller for servicing > */ > - ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable, > + ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable, > TRP0_INTERRUPT_ENABLE, > TRP0_INTERRUPT_ENABLE); > if (ret) > @@ -113,7 +113,7 @@ static int qcom_llcc_core_setup(struct llcc_drv_data *drv, struct regmap *llcc_b > if (ret) > return ret; > > - ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_2_enable, > + ret = regmap_update_bits(llcc_bcast_regmap, drv->edac_reg_offset->cmn_interrupt_0_enable, > DRP0_INTERRUPT_ENABLE, > DRP0_INTERRUPT_ENABLE); > if (ret) > -- > 2.46.0 > -- மணிவண்ணன் சதாசிவம்