From: Yicong Yang <yangyicong@huawei.com>
To: <will@kernel.org>, <mark.rutland@arm.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>
Cc: <jonathan.cameron@huawei.com>, <prime.zeng@hisilicon.com>,
<linuxarm@huawei.com>, <yangyicong@hisilicon.com>,
<wangyushan12@huawei.com>
Subject: [PATCH 7/9] drivers/perf: hisi: Support PMUs with no interrupt
Date: Tue, 18 Feb 2025 17:19:58 +0800 [thread overview]
Message-ID: <20250218092000.41641-8-yangyicong@huawei.com> (raw)
In-Reply-To: <20250218092000.41641-1-yangyicong@huawei.com>
From: Yicong Yang <yangyicong@hisilicon.com>
We'll have PMUs don't have an interrupt to indicate the counter
overflow, but the Uncore PMU core assume all the PMUs have
interrupt. So handle this case in the core. The existing PMUs
won't be affected.
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
drivers/perf/hisilicon/hisi_uncore_pmu.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/perf/hisilicon/hisi_uncore_pmu.c b/drivers/perf/hisilicon/hisi_uncore_pmu.c
index ef058b1dd509..a449651f79c9 100644
--- a/drivers/perf/hisilicon/hisi_uncore_pmu.c
+++ b/drivers/perf/hisilicon/hisi_uncore_pmu.c
@@ -510,7 +510,9 @@ int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
return 0;
hisi_pmu->on_cpu = cpumask_local_spread(0, dev_to_node(hisi_pmu->dev));
- WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(hisi_pmu->on_cpu)));
+ if (hisi_pmu->irq > 0)
+ WARN_ON(irq_set_affinity(hisi_pmu->irq,
+ cpumask_of(hisi_pmu->on_cpu)));
return 0;
}
@@ -525,7 +527,8 @@ int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
hisi_pmu->on_cpu = cpu;
/* Overflow interrupt also should use the same CPU */
- WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
+ if (hisi_pmu->irq > 0)
+ WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
return 0;
}
@@ -560,7 +563,9 @@ int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
/* Use this CPU for event counting */
hisi_pmu->on_cpu = target;
- WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
+
+ if (hisi_pmu->irq > 0)
+ WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
return 0;
}
--
2.24.0
next prev parent reply other threads:[~2025-02-18 9:19 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-18 9:19 [PATCH 0/9] General updates and two new drivers for HiSilicon Uncore PMU Yicong Yang
2025-02-18 9:19 ` [PATCH 1/9] drivers/perf: hisi: Extend struct hisi_pmu_dev_info Yicong Yang
2025-03-01 6:23 ` Will Deacon
2025-03-03 14:43 ` Yicong Yang
2025-03-04 9:21 ` Jonathan Cameron
2025-02-18 9:19 ` [PATCH 2/9] drivers/perf: hisi: Simplify the probe process for each DDRC version Yicong Yang
2025-03-04 9:26 ` Jonathan Cameron
2025-02-18 9:19 ` [PATCH 3/9] drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver Yicong Yang
2025-03-04 9:27 ` Jonathan Cameron
2025-02-18 9:19 ` [PATCH 4/9] drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information Yicong Yang
2025-03-01 6:43 ` Will Deacon
2025-03-04 9:49 ` Jonathan Cameron
2025-03-04 10:00 ` Jonathan Cameron
2025-02-18 9:19 ` [PATCH 5/9] drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver Yicong Yang
2025-03-04 10:02 ` Jonathan Cameron
2025-02-18 9:19 ` [PATCH 6/9] drivers/perf: hisi: Relax the event number check of v2 PMUs Yicong Yang
2025-03-04 10:11 ` Jonathan Cameron
2025-02-18 9:19 ` Yicong Yang [this message]
2025-03-04 10:16 ` [PATCH 7/9] drivers/perf: hisi: Support PMUs with no interrupt Jonathan Cameron
2025-02-18 9:19 ` [PATCH 8/9] drivers/perf: hisi: Add support for HiSilicon NoC PMU Yicong Yang
2025-03-04 10:22 ` Jonathan Cameron
2025-02-18 9:20 ` [PATCH 9/9] drivers/perf: hisi: Add support for HiSilicon MN PMU driver Yicong Yang
2025-03-04 10:24 ` Jonathan Cameron
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