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Tue, 18 Feb 2025 23:49:20 -0800 (PST) Date: Wed, 19 Feb 2025 13:19:13 +0530 From: Manivannan Sadhasivam To: Frank Li Cc: Shuai Xue , Jing Zhang , Will Deacon , Mark Rutland , Jingoo Han , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Shradha Todi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 0/4] PCI: dwc: Add PTM sysfs support Message-ID: <20250219074913.e4rtyup3m3yv66po@thinkpad> References: <20250218-pcie-qcom-ptm-v1-0-16d7e480d73e@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Tue, Feb 18, 2025 at 11:17:03AM -0500, Frank Li wrote: > On Tue, Feb 18, 2025 at 08:06:39PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > > Hi, > > > > This series adds sysfs support for PCIe PTM in Synopsys Designware IPs. > > > > First patch moves the common DWC struct definitions (dwc_pcie_vsec_id) to > > include/pci/pcie-dwc.h from dwc-pcie-pmu driver. This allows reusing the same > > definitions in pcie-designware-sysfs driver introduced in this series and also > > in the debugfs series by Shradha [1]. > > > > Second patch adds support for searching the Vendor Specific Extended Capability > > (VSEC) in the pcie-designware driver. This patch was originally based on > > Shradha's patch [2], but modified to accept 'struct dwc_pcie_vsec_id' to avoid > > iterating through the vsec_ids in the driver. > > > > Third patch adds the actual sysfs support for PTM in a new file > > pcie-designware-sysfs.c built along with pcie-designware.c. > > > > Finally, fourth patch masks the PTM_UPDATING interrupt in the pcie-qcom-ep > > driver to avoid processing the interrupt for each PTM context update. > > > > Testing > > ======= > > > > This series is tested on Qcom SA8775p Ride Mx platform where one SA8775p acts as > > RC and another as EP with following instructions: > > > > RC > > -- > > > > $ echo 1 > /sys/devices/platform/1c10000.pcie/dwc/ptm/ptm_context_valid > > > > EP > > -- > > > > $ echo auto > /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_context_update > > > > $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_local_clock > > 159612570424 > > > > $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_master_clock > > 159609466232 > > > > $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_t1 > > 159609466112 > > > > $ cat /sys/devices/platform/1c10000.pcie-ep/dwc/ptm/ptm_t4 > > 159609466518 > > > I am not sure what real means by only show these number. These values are supposed to be consumed by the userspace applications to make sure that whether the PTM feature is working as expected or not. For instance, once the PTM dialog is established with PTM root, PTM requester's local clock should be synchronized with PTM master clock. And these can be verified using these sysfs attributes. > It is quite > similar to network 1588, ptp. There were already linux-ptp > https://www.kernel.org/doc/html/v5.5/driver-api/ptp.html > PTP and PTM are different even though both are meant to synchronize times across devices. PTM is limited to PCIe hierarchy and the actual synchronization is performed at the hw level, limited to PCIe clock source (core_clk in DWC terms). > Can we use similar method to sync local timer to master? I think it is real > purpuse of PTM. > Actual synchronization happens in the hardware itself as I explained above. Software is not intended to do anything (if not using any external master clock source) to synchronize the clocks. I think you are referring to synchronizing the global clock source (the one used by the kernel) of the endpoint based on PTM. But I don't think that is what intended by this feature. - Mani -- மணிவண்ணன் சதாசிவம்