From: Abel Vesa <abel.vesa@linaro.org>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: Johan Hovold <johan@kernel.org>,
Stephan Gerhold <stephan.gerhold@linaro.org>,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Abel Vesa <abel.vesa@linaro.org>
Subject: [PATCH v2] arm64: dts: qcom: x1e80100: Add crypto engine
Date: Fri, 21 Feb 2025 15:07:03 +0200 [thread overview]
Message-ID: <20250221-x1e80100-crypto-v2-1-413ecf68dcd7@linaro.org> (raw)
On X Elite, there is a crypto engine IP block similar to ones found on
SM8x50 platforms.
Describe the crypto engine and its BAM.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
The dt-binding schema update for the x1e80100 compatible is here
(already picked up):
https://lore.kernel.org/all/20250213-dt-bindings-qcom-qce-x1e80100-v1-1-d17ef73a1c12@linaro.org/
---
Changes in v2:
- Added EE and channels numbers in BAM node, like Stephan suggested.
- Added v1.7.4 compatible as well.
- Link to v1: https://lore.kernel.org/r/20250213-x1e80100-crypto-v1-1-f93afdd4025a@linaro.org
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 9d38436763432892ceef95daf0335d4cf446357c..71d5f5eed4511030a51fb12e453f603d294080cc 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3708,6 +3708,38 @@ pcie4_phy: phy@1c0e000 {
status = "disabled";
};
+ cryptobam: dma-controller@1dc4000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0 0x01dc4000 0 0x28000>;
+
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+
+ #dma-cells = <1>;
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+
+ qcom,ee = <0>;
+ qcom,num-ees = <7>;
+ num-channels = <30>;
+ qcom,controlled-remotely;
+ };
+
+ crypto: crypto@1dfa000 {
+ compatible = "qcom,x1e80100-qce", "qcom,sm8150-qce", "qcom,qce";
+ reg = <0 0x01dfa000 0 0x6000>;
+
+ interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "memory";
+
+ dmas = <&cryptobam 4>, <&cryptobam 5>;
+ dma-names = "rx", "tx";
+
+ iommus = <&apps_smmu 0x480 0>,
+ <&apps_smmu 0x481 0>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x20000>;
---
base-commit: d4b0fd87ff0d4338b259dc79b2b3c6f7e70e8afa
change-id: 20250213-x1e80100-crypto-18c7d14cd459
Best regards,
--
Abel Vesa <abel.vesa@linaro.org>
next reply other threads:[~2025-02-21 13:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-21 13:07 Abel Vesa [this message]
2025-02-21 18:11 ` Rob Herring (Arm)
2025-02-24 15:01 ` Stephan Gerhold
2025-11-16 22:23 ` Val Packett
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