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Sat, 22 Feb 2025 08:53:44 -0800 (PST) Date: Sat, 22 Feb 2025 22:23:38 +0530 From: Manivannan Sadhasivam To: Dmitry Baryshkov Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 8/8] arm64: dts: qcom: sm8450: add PCIe EP device nodes Message-ID: <20250222165338.oox3d63ven2kokez@thinkpad> References: <20250221-sar2130p-pci-v3-0-61a0fdfb75b4@linaro.org> <20250221-sar2130p-pci-v3-8-61a0fdfb75b4@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250221-sar2130p-pci-v3-8-61a0fdfb75b4@linaro.org> On Fri, Feb 21, 2025 at 05:52:06PM +0200, Dmitry Baryshkov wrote: > On the Qualcomm SM8450 platform the second PCIe host can be used > either as an RC or as an EP device. Add device node for the PCIe EP. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Manivannan Sadhasivam - Mani > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 62 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 9c809fc5fa45a98ff5441a0b6809931588897243..3783930d63a73158addc44d00d9da2efa0986a25 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -2262,6 +2262,68 @@ pcie@0 { > }; > }; > > + pcie1_ep: pcie-ep@1c08000 { > + compatible = "qcom,sm8450-pcie-ep"; > + reg = <0x0 0x01c08000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf1d>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x1000>, > + <0x0 0x40200000 0x0 0x1000000>, > + <0x0 0x01c0b000 0x0 0x1000>, > + <0x0 0x40002000 0x0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "addr_space", > + "mmio", > + "dma"; > + > + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, > + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "ref", > + "ddrss_sf_tbu", > + "aggre_noc_axi"; > + > + interrupts = , > + , > + ; > + interrupt-names = "global", > + "doorbell", > + "dma"; > + > + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "pcie-mem", > + "cpu-pcie"; > + > + iommus = <&apps_smmu 0x1c80 0x7f>; > + resets = <&gcc GCC_PCIE_1_BCR>; > + reset-names = "core"; > + power-domains = <&gcc PCIE_1_GDSC>; > + phys = <&pcie1_phy>; > + phy-names = "pciephy"; > + num-lanes = <2>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie1_default_state>; > + > + status = "disabled"; > + }; > + > pcie1_phy: phy@1c0e000 { > compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; > reg = <0 0x01c0e000 0 0x2000>; > > -- > 2.39.5 > -- மணிவண்ணன் சதாசிவம்