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Wed, 26 Feb 2025 19:59:32 -0800 (PST) Date: Thu, 27 Feb 2025 09:29:24 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , quic_vbadigan@quicnic.com, amitk@kernel.org, dmitry.baryshkov@linaro.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, Bartosz Golaszewski Subject: Re: [PATCH v4 00/10] PCI: Enable Power and configure the TC956x PCIe switch Message-ID: <20250227035924.p43tpbtjmqszdww6@thinkpad> References: <20250225-qps615_v4_1-v4-0-e08633a7bdf8@oss.qualcomm.com> <20250227035737.q7qlexdcieubbphx@thinkpad> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250227035737.q7qlexdcieubbphx@thinkpad> On Thu, Feb 27, 2025 at 09:27:47AM +0530, Manivannan Sadhasivam wrote: > On Tue, Feb 25, 2025 at 03:03:57PM +0530, Krishna Chaitanya Chundru wrote: > > TC956x is the PCIe switch which has one upstream and three downstream > > ports. To one of the downstream ports ethernet MAC is connected as endpoint > > device. Other two downstream ports are supposed to connect to external > > device. One Host can connect to TC956x by upstream port. > > > > TC956x switch power is controlled by the GPIO's. After powering on > > the switch will immediately participate in the link training. if the > > host is also ready by that time PCIe link will established. > > > > The TC956x needs to configured certain parameters like de-emphasis, > > disable unused port etc before link is established. > > > > As the controller starts link training before the probe of pwrctl driver, > > the PCIe link may come up as soon as we power on the switch. Due to this > > configuring the switch itself through i2c will not have any effect as > > this configuration needs to done before link training. To avoid this > > introduce two functions in pci_ops to start_link() & stop_link() which > > will disable the link training if the PCIe link is not up yet. > > > > Enable global IRQ for PCIe controller so that recan can happen when > > link was up through global IRQ. > > > > Move these patches to a separate series. > Or you can just drop them. I have a series that adds global IRQ to most of the SoCs and sc7280 is one of them. - Mani -- மணிவண்ணன் சதாசிவம்