From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m19731105.qiye.163.com (mail-m19731105.qiye.163.com [220.197.31.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 428A822F388 for ; Thu, 27 Feb 2025 11:08:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.105 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654498; cv=none; b=dzklH/4/XZF20jO4sU++rzHXxAwbf7orvvxAiMYyz81FEm68KenwkggCMomc8HAKXSxxZUXOIAM+R1CDzczCOjh5GsQdjMBoMU7K3qWs1lquC2+kQXCTAzwiqOq7tRu1AlwOIxDGaeB1wWj9b2WkWv8TYEFfvOzDbO5AwYDo8m4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740654498; c=relaxed/simple; bh=yyTB9zbkRqyr7pfLZIoqaAbFVOxqJX/Thf0DV8kx8w4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UCu6EUxw5btjJUMx6dst3CCwh/bAwpDx0Mm+43ancMB68lqrsMyorPBX6WC2QmTJCl4f3JLNOi0spBUrtGyQoF1RZhtCkrqiYLZqTNenSBLiGihNh4qMeyqt85t0qsK8Po2rq+SBv0nG/ili6nL+75xPCKz2UuGRSfYPdFKjH20= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=JBRaFI2y; arc=none smtp.client-ip=220.197.31.105 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="JBRaFI2y" Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id c65b37e0; Thu, 27 Feb 2025 19:08:06 +0800 (GMT+08:00) From: Kever Yang To: heiko@sntech.de Cc: linux-rockchip@lists.infradead.org, Finley Xiao , Kever Yang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v2 2/3] nvmem: rockchip-otp: Add support for rk3568-otp Date: Thu, 27 Feb 2025 19:08:03 +0800 Message-Id: <20250227110804.2342976-2-kever.yang@rock-chips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250227110804.2342976-1-kever.yang@rock-chips.com> References: <20250227110804.2342976-1-kever.yang@rock-chips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQklCTlYdQ05CGEhIGEtNGUlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpKQk 1VSktLVUpCWQY+ X-HM-Tid: 0a954717a42203afkunmc65b37e0 X-HM-MType: 1 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6PFE6LSo*KzIOAQ0vOBQLLi42 VlEKCxlVSlVKTE9LTU5PT0NMT0xOVTMWGhIXVRAeDR4JVQIaFRw7CRQYEFYYExILCFUYFBZFWVdZ EgtZQVlOQ1VJSVVMVUpKT1lXWQgBWUFIQkpNNwY+ DKIM-Signature:a=rsa-sha256; b=JBRaFI2yD2zp3y1ATQUcyc5yRbkCXTy5lqRarGWTK+cUsHYNTdDMiHN+8c+KN3Ls9kj7O/yYoAYX3v1OPxR3TK8uQNuSwv4XKRrqtN4tGksjfzh9Wzk/0zjqofd5/VCAktWDgy/f7Il0Fc0H9NNOl4OtIn5IXqUTw+zr4Ye0fzk=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=IrISmUSshV/Pl9SnXYyegDCizUHf7zu6Wx/WRBCGgHI=; h=date:mime-version:subject:message-id:from; From: Finley Xiao This adds the necessary data for handling efuse on the rk3568. Signed-off-by: Finley Xiao Signed-off-by: Kever Yang --- Changes in v2: None drivers/nvmem/rockchip-otp.c | 82 ++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/nvmem/rockchip-otp.c b/drivers/nvmem/rockchip-otp.c index ebc3f0b24166..a04bce89ecc8 100644 --- a/drivers/nvmem/rockchip-otp.c +++ b/drivers/nvmem/rockchip-otp.c @@ -27,6 +27,7 @@ #define OTPC_USER_CTRL 0x0100 #define OTPC_USER_ADDR 0x0104 #define OTPC_USER_ENABLE 0x0108 +#define OTPC_USER_QP 0x0120 #define OTPC_USER_Q 0x0124 #define OTPC_INT_STATUS 0x0304 #define OTPC_SBPI_CMD0_OFFSET 0x1000 @@ -53,6 +54,8 @@ #define SBPI_ENABLE_MASK GENMASK(16, 16) #define OTPC_TIMEOUT 10000 +#define OTPC_TIMEOUT_PROG 100000 +#define RK3568_NBYTES 2 /* RK3588 Register */ #define RK3588_OTPC_AUTO_CTRL 0x04 @@ -184,6 +187,70 @@ static int px30_otp_read(void *context, unsigned int offset, return ret; } +static int rk3568_otp_read(void *context, unsigned int offset, void *val, + size_t bytes) +{ + struct rockchip_otp *otp = context; + unsigned int addr_start, addr_end, addr_offset, addr_len; + unsigned int otp_qp; + u32 out_value; + u8 *buf; + int ret = 0, i = 0; + + addr_start = rounddown(offset, RK3568_NBYTES) / RK3568_NBYTES; + addr_end = roundup(offset + bytes, RK3568_NBYTES) / RK3568_NBYTES; + addr_offset = offset % RK3568_NBYTES; + addr_len = addr_end - addr_start; + + buf = kzalloc(array3_size(addr_len, RK3568_NBYTES, sizeof(*buf)), + GFP_KERNEL); + if (!buf) + return -ENOMEM; + + ret = rockchip_otp_reset(otp); + if (ret) { + dev_err(otp->dev, "failed to reset otp phy\n"); + return ret; + } + + ret = rockchip_otp_ecc_enable(otp, true); + if (ret < 0) { + dev_err(otp->dev, "rockchip_otp_ecc_enable err\n"); + return ret; + } + + writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); + udelay(5); + while (addr_len--) { + writel(addr_start++ | OTPC_USER_ADDR_MASK, + otp->base + OTPC_USER_ADDR); + writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK, + otp->base + OTPC_USER_ENABLE); + ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE); + if (ret < 0) { + dev_err(otp->dev, "timeout during read setup\n"); + goto read_end; + } + otp_qp = readl(otp->base + OTPC_USER_QP); + if (((otp_qp & 0xc0) == 0xc0) || (otp_qp & 0x20)) { + ret = -EIO; + dev_err(otp->dev, "ecc check error during read setup\n"); + goto read_end; + } + out_value = readl(otp->base + OTPC_USER_Q); + memcpy(&buf[i], &out_value, RK3568_NBYTES); + i += RK3568_NBYTES; + } + + memcpy(val, buf + addr_offset, bytes); + +read_end: + writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL); + kfree(buf); + + return ret; +} + static int rk3588_otp_read(void *context, unsigned int offset, void *val, size_t bytes) { @@ -274,6 +341,17 @@ static const struct rockchip_data px30_data = { .reg_read = px30_otp_read, }; +static const char * const rk3568_otp_clocks[] = { + "usr", "sbpi", "apb_pclk", "phy", +}; + +static const struct rockchip_data rk3568_data = { + .size = 0x80, + .clks = rk3568_otp_clocks, + .num_clks = ARRAY_SIZE(rk3568_otp_clocks), + .reg_read = rk3568_otp_read, +}; + static const char * const rk3588_otp_clocks[] = { "otp", "apb_pclk", "phy", "arb", }; @@ -294,6 +372,10 @@ static const struct of_device_id rockchip_otp_match[] = { .compatible = "rockchip,rk3308-otp", .data = &px30_data, }, + { + .compatible = "rockchip,rk3568-otp", + .data = &rk3568_data, + }, { .compatible = "rockchip,rk3588-otp", .data = &rk3588_data, -- 2.25.1