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([49.37.249.43]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-223504c5bddsm13219135ad.140.2025.02.27.04.36.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Feb 2025 04:36:59 -0800 (PST) From: Himanshu Chauhan To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-efi@vger.kernel.org, acpica-devel@lists.linux.dev Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, lenb@kernel.org, james.morse@arm.com, tony.luck@intel.com, ardb@kernel.org, conor@kernel.org, cleger@rivosinc.com, robert.moore@intel.com, sunilvl@ventanamicro.com, apatel@ventanamicro.com, Himanshu Chauhan Subject: [RFC PATCH v1 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts Date: Thu, 27 Feb 2025 18:06:22 +0530 Message-ID: <20250227123628.2931490-5-hchauhan@ventanamicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227123628.2931490-1-hchauhan@ventanamicro.com> References: <20250227123628.2931490-1-hchauhan@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit GHES error handling requires fixmap entries for IRQ notifications. Add fixmap indices for IRQ, SSE Low and High priority notifications. Signed-off-by: Himanshu Chauhan --- arch/riscv/include/asm/fixmap.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h index 0a55099bb734..fa3a0ec0c55c 100644 --- a/arch/riscv/include/asm/fixmap.h +++ b/arch/riscv/include/asm/fixmap.h @@ -38,6 +38,14 @@ enum fixed_addresses { FIX_TEXT_POKE0, FIX_EARLYCON_MEM_BASE, +#ifdef CONFIG_ACPI_APEI_GHES + /* Used for GHES mapping from assorted contexts */ + FIX_APEI_GHES_IRQ, +#ifdef CONFIG_RISCV_SSE + FIX_APEI_GHES_SSE_LOW_PRIORITY, + FIX_APEI_GHES_SSE_HIGH_PRIORITY, +#endif /* CONFIG_RISCV_SSE */ +#endif /* CONFIG_ACPI_APEI_GHES */ __end_of_permanent_fixed_addresses, /* * Temporary boot-time mappings, used by early_ioremap(), -- 2.43.0