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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for configuring counters for 32-bit EL0 to allow adding support for implementations with 32-bit EL0. For documentation purposes, also add the bitmask for configuring counters for 64-bit EL3. Signed-off-by: Nick Chan --- arch/arm64/include/asm/apple_m1_pmu.h | 3 +++ drivers/perf/apple_m1_cpu_pmu.c | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm/apple_m1_pmu.h index 99483b19b99fca38483faad443ad4bcf4b85ef63..75be4b4c71f167a6874e22b38dc7c0bf30d25a47 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -37,8 +37,11 @@ #define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44) #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) +#define PMCR1_COUNT_A32_EL0_0_7 GENMASK(7, 0) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) +#define PMCR1_COUNT_A64_EL3_0_7 GENMASK(31, 24) +#define PMCR1_COUNT_A32_EL0_8_9 GENMASK(33, 32) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) #define PMCR1_COUNT_A64_EL1_8_9 GENMASK(49, 48) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pmu.c index bf397fd81230007dcf52888f148e3158dc02e29d..73ba9861a15ff931b5e388b6d809dedb140e2292 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -335,10 +335,16 @@ static void m1_pmu_configure_counter(unsigned int index, u8 event, case 0 ... 7: user_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7)); kernel_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7)); + + if (system_supports_32bit_el0()) + user_bit |= BIT(get_bit_offset(index, PMCR1_COUNT_A32_EL0_0_7)); break; case 8 ... 9: user_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9)); kernel_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9)); + + if (system_supports_32bit_el0()) + user_bit |= BIT(get_bit_offset(index - 8, PMCR1_COUNT_A32_EL0_8_9)); break; default: BUG(); -- 2.48.1