From: niravkumar.l.rabara@intel.com
To: Dinh Nguyen <dinguyen@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
niravkumar.l.rabara@intel.com, nirav.rabara@altera.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Subject: [PATCH RESEND v3 2/2] arm64: dts: socfpga: agilex5: add clock-names property to nand node
Date: Fri, 28 Feb 2025 12:53:49 +0800 [thread overview]
Message-ID: <20250228045349.1429680-1-niravkumar.l.rabara@intel.com> (raw)
From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Add required clock-names property to the nand node.
Fixes: 2d599bc43813 (arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 51c6e19e40b8..27f75e1bc8eb 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -271,6 +271,7 @@ nand: nand-controller@10b80000 {
#size-cells = <0>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
+ clock-names = "nf_clk";
cdns,board-delay-ps = <4830>;
status = "disabled";
};
--
2.25.1
next reply other threads:[~2025-02-28 4:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-28 4:53 niravkumar.l.rabara [this message]
2025-03-04 12:48 ` Dinh Nguyen
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