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From: "Xin Li (Intel)" <xin@zytor.com>
To: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
	dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com,
	will@kernel.org, peterz@infradead.org, yury.norov@gmail.com,
	akpm@linux-foundation.org, acme@kernel.org, namhyung@kernel.org,
	brgerst@gmail.com, andrew.cooper3@citrix.com,
	nik.borisov@suse.com
Subject: [PATCH v6 1/5] x86/cpufeatures: Rename X86_CMPXCHG64 to X86_CX8
Date: Fri, 28 Feb 2025 00:23:34 -0800	[thread overview]
Message-ID: <20250228082338.73859-2-xin@zytor.com> (raw)
In-Reply-To: <20250228082338.73859-1-xin@zytor.com>

From: "H. Peter Anvin (Intel)" <hpa@zytor.com>

Replace X86_CMPXCHG64 with X86_CX8, as CX8 is the name of the CPUID
flag, thus to make it consistent with X86_FEATURE_CX8 defined in
<asm/cpufeatures.h>.

No functional change intended.

Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
---

Change in v6:
* Rename X86_CMPXCHG64 in a separate patch (Borislav Petkov).
---
 arch/x86/Kconfig                               | 2 +-
 arch/x86/Kconfig.cpu                           | 4 ++--
 arch/x86/include/asm/asm-prototypes.h          | 2 +-
 arch/x86/include/asm/atomic64_32.h             | 2 +-
 arch/x86/include/asm/cmpxchg_32.h              | 2 +-
 arch/x86/include/asm/required-features.h       | 2 +-
 arch/x86/lib/Makefile                          | 2 +-
 arch/x86/lib/cmpxchg8b_emu.S                   | 2 +-
 lib/atomic64_test.c                            | 2 +-
 tools/arch/x86/include/asm/required-features.h | 2 +-
 10 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 60c2a16c7801..1e50da06ffc4 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -133,7 +133,7 @@ config X86
 	select ARCH_SUPPORTS_AUTOFDO_CLANG
 	select ARCH_SUPPORTS_PROPELLER_CLANG    if X86_64
 	select ARCH_USE_BUILTIN_BSWAP
-	select ARCH_USE_CMPXCHG_LOCKREF		if X86_CMPXCHG64
+	select ARCH_USE_CMPXCHG_LOCKREF		if X86_CX8
 	select ARCH_USE_MEMTEST
 	select ARCH_USE_QUEUED_RWLOCKS
 	select ARCH_USE_QUEUED_SPINLOCKS
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 8fcb8ccee44b..f8b3296fe2e1 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -299,7 +299,7 @@ config X86_HAVE_PAE
 	def_bool y
 	depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64
 
-config X86_CMPXCHG64
+config X86_CX8
 	def_bool y
 	depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 || MGEODEGX1 || MGEODE_LX
 
@@ -313,7 +313,7 @@ config X86_MINIMUM_CPU_FAMILY
 	int
 	default "64" if X86_64
 	default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MK7)
-	default "5" if X86_32 && X86_CMPXCHG64
+	default "5" if X86_32 && X86_CX8
 	default "4"
 
 config X86_DEBUGCTLMSR
diff --git a/arch/x86/include/asm/asm-prototypes.h b/arch/x86/include/asm/asm-prototypes.h
index 3674006e3974..8d9e62725202 100644
--- a/arch/x86/include/asm/asm-prototypes.h
+++ b/arch/x86/include/asm/asm-prototypes.h
@@ -16,7 +16,7 @@
 #include <asm/gsseg.h>
 #include <asm/nospec-branch.h>
 
-#ifndef CONFIG_X86_CMPXCHG64
+#ifndef CONFIG_X86_CX8
 extern void cmpxchg8b_emu(void);
 #endif
 
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
index 6c6e9b9f98a4..797085ecaaa4 100644
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -48,7 +48,7 @@ static __always_inline s64 arch_atomic64_read_nonatomic(const atomic64_t *v)
 	ATOMIC64_EXPORT(atomic64_##sym)
 #endif
 
-#ifdef CONFIG_X86_CMPXCHG64
+#ifdef CONFIG_X86_CX8
 #define __alternative_atomic64(f, g, out, in...) \
 	asm volatile("call %c[func]" \
 		     : ALT_OUTPUT_SP(out) \
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index 95b5f990ca88..ee89fbc4dd4b 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -69,7 +69,7 @@ static __always_inline bool __try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp,
 	return __arch_try_cmpxchg64(ptr, oldp, new,);
 }
 
-#ifdef CONFIG_X86_CMPXCHG64
+#ifdef CONFIG_X86_CX8
 
 #define arch_cmpxchg64 __cmpxchg64
 
diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h
index e9187ddd3d1f..0068133cb622 100644
--- a/arch/x86/include/asm/required-features.h
+++ b/arch/x86/include/asm/required-features.h
@@ -23,7 +23,7 @@
 # define NEED_PAE	0
 #endif
 
-#ifdef CONFIG_X86_CMPXCHG64
+#ifdef CONFIG_X86_CX8
 # define NEED_CX8	(1<<(X86_FEATURE_CX8 & 31))
 #else
 # define NEED_CX8	0
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index f453507649d4..64ccecedc9f8 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -56,7 +56,7 @@ ifeq ($(CONFIG_X86_32),y)
         lib-y += string_32.o
         lib-y += memmove_32.o
         lib-y += cmpxchg8b_emu.o
-ifneq ($(CONFIG_X86_CMPXCHG64),y)
+ifneq ($(CONFIG_X86_CX8),y)
         lib-y += atomic64_386_32.o
 endif
 else
diff --git a/arch/x86/lib/cmpxchg8b_emu.S b/arch/x86/lib/cmpxchg8b_emu.S
index 1c96be769adc..d4bb24347ff8 100644
--- a/arch/x86/lib/cmpxchg8b_emu.S
+++ b/arch/x86/lib/cmpxchg8b_emu.S
@@ -7,7 +7,7 @@
 
 .text
 
-#ifndef CONFIG_X86_CMPXCHG64
+#ifndef CONFIG_X86_CX8
 
 /*
  * Emulate 'cmpxchg8b (%esi)' on UP
diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index 759ea1783cc5..d726068358c7 100644
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -254,7 +254,7 @@ static __init int test_atomics_init(void)
 	pr_info("passed for %s platform %s CX8 and %s SSE\n",
 #ifdef CONFIG_X86_64
 		"x86-64",
-#elif defined(CONFIG_X86_CMPXCHG64)
+#elif defined(CONFIG_X86_CX8)
 		"i586+",
 #else
 		"i386+",
diff --git a/tools/arch/x86/include/asm/required-features.h b/tools/arch/x86/include/asm/required-features.h
index e9187ddd3d1f..0068133cb622 100644
--- a/tools/arch/x86/include/asm/required-features.h
+++ b/tools/arch/x86/include/asm/required-features.h
@@ -23,7 +23,7 @@
 # define NEED_PAE	0
 #endif
 
-#ifdef CONFIG_X86_CMPXCHG64
+#ifdef CONFIG_X86_CX8
 # define NEED_CX8	(1<<(X86_FEATURE_CX8 & 31))
 #else
 # define NEED_CX8	0
-- 
2.48.1


  reply	other threads:[~2025-02-28  8:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-28  8:23 [PATCH v6 0/5] x86/cpufeatures: Automatically generate required and disabled feature masks Xin Li (Intel)
2025-02-28  8:23 ` Xin Li (Intel) [this message]
2025-02-28 16:53   ` [tip: x86/cpu] x86/cpufeatures: Rename X86_CMPXCHG64 to X86_CX8 tip-bot2 for H. Peter Anvin (Intel)
2025-02-28  8:23 ` [PATCH v6 2/5] x86/cpufeatures: Add {required,disabled} feature configs Xin Li (Intel)
2025-02-28 16:53   ` [tip: x86/cpu] " tip-bot2 for H. Peter Anvin (Intel)
2025-03-10  8:18   ` [tip: x86/cpu] x86/cpufeatures: Add {REQUIRED,DISABLED} " tip-bot2 for H. Peter Anvin (Intel)
2025-03-10 14:43     ` H. Peter Anvin
2025-03-10 15:06       ` Borislav Petkov
2025-03-10 18:57       ` Ingo Molnar
2025-03-19 11:04   ` [tip: x86/core] " tip-bot2 for H. Peter Anvin (Intel)
2025-02-28  8:23 ` [PATCH v6 3/5] x86/cpufeatures: Generate a feature mask header based on build config Xin Li (Intel)
2025-02-28 16:53   ` [tip: x86/cpu] " tip-bot2 for H. Peter Anvin (Intel)
2025-03-03 11:38   ` [PATCH v6 3/5] " Aithal, Srikanth
2025-03-03 12:05     ` H. Peter Anvin
2025-03-03 13:25       ` Borislav Petkov
2025-03-03 22:34         ` H. Peter Anvin
2025-03-04 10:18         ` Xin Li
2025-03-04 10:29           ` Borislav Petkov
2025-03-05  7:30             ` Xin Li
2025-03-05 22:04               ` Borislav Petkov
2025-03-22 19:58                 ` Xin Li
2025-02-28  8:23 ` [PATCH v6 4/5] x86/cpufeatures: Remove {disabled,required}-features.h Xin Li (Intel)
2025-02-28 16:53   ` [tip: x86/cpu] " tip-bot2 for Xin Li (Intel)
2025-02-28  8:23 ` [PATCH v6 5/5] x86/cpufeatures: Use AWK to generate {REQUIRED|DISABLED}_MASK_BIT_SET Xin Li (Intel)
2025-02-28 16:53   ` [tip: x86/cpu] " tip-bot2 for Xin Li (Intel)
2025-03-10  8:18   ` [tip: x86/cpu] x86/cpufeatures: Use AWK to generate {REQUIRED|DISABLED}_MASK_BIT_SET in <asm/cpufeaturemasks.h> tip-bot2 for Xin Li (Intel)
2025-03-19 11:03   ` [tip: x86/core] " tip-bot2 for Xin Li (Intel)
2025-02-28  9:26 ` [PATCH v6 0/5] x86/cpufeatures: Automatically generate required and disabled feature masks Ingo Molnar

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