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Peter Anvin" , Andrew Cooper , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings Date: Tue, 4 Mar 2025 09:51:11 +0100 Message-ID: <20250304085152.51092-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi, As part of the onging x86-cpuid work [*], we've found that the handling of leaf 0x2 and leaf 0x4 code paths is difficult to work with in its current state. This was mostly due to the organic growth of the x86/cpu and x86/cacheinfo logic since its very early Linux days. This series cleans up and refactors these code paths in preparation for the new x86-cpuid model. Summary: - Patches 1 to 3 are independent bugfixes that were discovered during this refactoring work. - Patches 4 to 10 are x86/cpu refactorings for code size and readability. - Patch 10 adds standardized and kernel-doc documented logic for accessing leaf 0x2 one byte descriptors. This makes the leaf 0x2 sanitization logic centralized in one place. x86/cpu and x86/cacheinfo is modified to use such macros afterwards. - Patches 11 to 28 refactors the x86/cacheinfo code. Beside readability, some of the unrelated logic (e.g. AMD northbridge cache_disable sysfs code) was first splitted from the generic leaf 0x4 code paths, at the structure relationships level, then gutted-out into their own files. - Patches 29 to 31 consolidate the existing (loop-based lookup) leaf 0x2 cache and TLB descriptor tables into one hash-based lookup table. This reduces code size while still keeping rodata size in check. Standardized macros for accessing this consolidated table are also added. Call sites can now just do: const struct leaf_0x2_table *entry; union leaf_0x2_regs regs; u8 *ptr; get_leaf_0x2_regs(®s); for_each_leaf_0x2_entry(regs, ptr, entry) { switch (entry->c_type) { ... } } without need to worry about sanitizing registers, skipping certain descriptors, etc. - Patches 32 and 33 uses the consolidated table above for x86/cpu and x86/cacheinfo. - Patches 34 to 40 provide the final set of x86/refactorings. This series is based on -rc5. It also applies cleanly on top of tip/x86/core. Note, testing was done by comparing below files: /proc/cpuinfo /sys/devices/system/cpu/ /sys/kernel/debug/x86/topo/ dmesg --notime | grep 'Last level [id]TLB entries' before and after on various old and new x86 machine configurations. [*] https://gitlab.com/x86-cpuid.org/x86-cpuid-db https://x86-cpuid.org 8<----- Ahmed S. Darwish (33): x86/cacheinfo: Validate cpuid leaf 0x2 EDX output x86/cpu: Validate cpuid leaf 0x2 EDX output x86/cpu: Properly parse leaf 0x2 TLB descriptor 0x63 x86/cpuid: Include linux/build_bug.h x86/cpu: Remove unnecessary headers and reorder the rest x86/cpu: Use max() for leaf 0x2 TLB descriptors parsing x86/cpu: Simplify TLB entry count storage x86/cpu: Remove leaf 0x2 parsing loop and add helpers x86/cacheinfo: Remove unnecessary headers and reorder the rest x86/cacheinfo: Use cpuid leaf 0x2 parsing helpers x86/cacheinfo: Constify _cpuid4_info_regs instances x86/cacheinfo: Align ci_info_init() assignment expressions x86/cacheinfo: Standardize _cpuid4_info_regs instance naming x86: treewide: Introduce x86_vendor_amd_or_hygon() x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors x86/cacheinfo: Use enums for cache descriptor types x86/cpu: Use enums for TLB descriptor types sizes.h: Cover all possible x86 cpu cache sizes x86/cacheinfo: Use consolidated leaf 0x2 descriptor table x86/cpu: Use consolidated leaf 0x2 descriptor table x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic x86/cacheinfo: Separate intel leaf 0x4 handling x86/cacheinfo: Extract out cache level topology ID calculation x86/cacheinfo: Extract out cache self-snoop checks x86/cacheinfo: Relocate leaf 0x4 cache_type mapping x86/cacheinfo: Introduce amd_hygon_cpu_has_l3_cache() x86/cacheinfo: Apply maintainer-tip coding style fixes Thomas Gleixner (7): x86/cpu: Get rid of smp_store_cpu_info() indirection x86/cpu: Remove unused TLB strings x86/cacheinfo: Remove the P4 trace leftovers for real x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup x86/cacheinfo: Properly name amd_cpuid4()'s first parameter x86/cacheinfo: Use proper name for cacheinfo instances x86/cpu: Consolidate CPUID leaf 0x2 tables arch/x86/events/amd/uncore.c | 3 +- arch/x86/events/rapl.c | 3 +- arch/x86/include/asm/cpuid.h | 1 + arch/x86/include/asm/cpuid/types.h | 173 ++++ arch/x86/include/asm/processor.h | 26 +- arch/x86/include/asm/smp.h | 2 - arch/x86/kernel/amd_nb.c | 16 +- arch/x86/kernel/cpu/Makefile | 5 +- arch/x86/kernel/cpu/amd.c | 18 +- arch/x86/kernel/cpu/amd_cache_disable.c | 301 +++++++ arch/x86/kernel/cpu/bugs.c | 12 +- arch/x86/kernel/cpu/cacheinfo.c | 1062 +++++++---------------- arch/x86/kernel/cpu/common.c | 31 +- arch/x86/kernel/cpu/cpu.h | 17 +- arch/x86/kernel/cpu/cpuid_0x2_table.c | 128 +++ arch/x86/kernel/cpu/hygon.c | 16 +- arch/x86/kernel/cpu/intel.c | 208 ++--- arch/x86/kernel/cpu/mce/core.c | 4 +- arch/x86/kernel/cpu/mce/severity.c | 3 +- arch/x86/kernel/cpu/mtrr/cleanup.c | 3 +- arch/x86/kernel/smpboot.c | 27 +- arch/x86/kvm/svm/svm.c | 3 +- arch/x86/pci/amd_bus.c | 3 +- arch/x86/xen/enlighten.c | 15 +- arch/x86/xen/pmu.c | 3 +- arch/x86/xen/smp_pv.c | 2 +- include/linux/sizes.h | 8 + 27 files changed, 1076 insertions(+), 1017 deletions(-) create mode 100644 arch/x86/include/asm/cpuid/types.h create mode 100644 arch/x86/kernel/cpu/amd_cache_disable.c create mode 100644 arch/x86/kernel/cpu/cpuid_0x2_table.c base-commit: 7eb172143d5508b4da468ed59ee857c6e5e01da6 -- 2.48.1