From: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
To: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc: boris.brezillon@collabora.com, robh@kernel.org,
steven.price@arm.com, maarten.lankhorst@linux.intel.com,
mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com,
simona@ffwll.ch, kernel@collabora.com,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, sjoerd@collabora.com,
Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Subject: [PATCH v1 3/6] drm/panfrost: Unify panfrost_mmu_enable/disable common code
Date: Mon, 10 Mar 2025 16:59:18 -0300 [thread overview]
Message-ID: <20250310195921.157511-4-ariel.dalessandro@collabora.com> (raw)
In-Reply-To: <20250310195921.157511-1-ariel.dalessandro@collabora.com>
Both these functions write to MMU_AS_CONTROL register in the same way.
Define a common _panfrost_mmu_as_control_write function with the shared
code.
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
---
drivers/gpu/drm/panfrost/panfrost_mmu.c | 33 ++++++++++++-------------
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/panfrost/panfrost_mmu.c b/drivers/gpu/drm/panfrost/panfrost_mmu.c
index 294f86b3c25e7..31df3a96f89bd 100644
--- a/drivers/gpu/drm/panfrost/panfrost_mmu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_mmu.c
@@ -121,38 +121,37 @@ static int mmu_hw_do_operation(struct panfrost_device *pfdev,
return ret;
}
-static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
+static void
+_panfrost_mmu_as_control_write(struct panfrost_device *pfdev, u32 as_nr,
+ u64 transtab, u64 memattr)
{
- int as_nr = mmu->as;
- struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg;
- u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
- u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
-
mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), lower_32_bits(transtab));
mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), upper_32_bits(transtab));
- /* Need to revisit mem attrs.
- * NC is the default, Mali driver is inner WT.
- */
mmu_write(pfdev, AS_MEMATTR_LO(as_nr), lower_32_bits(memattr));
mmu_write(pfdev, AS_MEMATTR_HI(as_nr), upper_32_bits(memattr));
write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
}
-static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
+static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
{
- mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
-
- mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
- mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
+ int as_nr = mmu->as;
+ struct io_pgtable_cfg *cfg = &mmu->pgtbl_cfg;
+ u64 transtab = cfg->arm_mali_lpae_cfg.transtab;
+ u64 memattr = cfg->arm_mali_lpae_cfg.memattr;
- mmu_write(pfdev, AS_MEMATTR_LO(as_nr), 0);
- mmu_write(pfdev, AS_MEMATTR_HI(as_nr), 0);
+ /* Need to revisit mem attrs.
+ * NC is the default, Mali driver is inner WT.
+ */
+ _panfrost_mmu_as_control_write(pfdev, as_nr, transtab, memattr);
+}
- write_cmd(pfdev, as_nr, AS_COMMAND_UPDATE);
+static void panfrost_mmu_disable(struct panfrost_device *pfdev, u32 as_nr)
+{
+ _panfrost_mmu_as_control_write(pfdev, as_nr, 0, 0);
}
u32 panfrost_mmu_as_get(struct panfrost_device *pfdev, struct panfrost_mmu *mmu)
--
2.47.2
next prev parent reply other threads:[~2025-03-10 20:00 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-10 19:59 [PATCH v1 0/6] drm/panfrost: Add support for AARCH64_4K page table format Ariel D'Alessandro
2025-03-10 19:59 ` [PATCH v1 1/6] drm/panfrost: Set IOMMU_CACHE flag Ariel D'Alessandro
2025-03-11 9:16 ` AngeloGioacchino Del Regno
2025-03-14 16:17 ` Steven Price
2025-03-10 19:59 ` [PATCH v1 2/6] drm/panfrost: Use GPU_MMU_FEATURES_VA_BITS/PA_BITS macros Ariel D'Alessandro
2025-03-10 19:59 ` Ariel D'Alessandro [this message]
2025-03-11 7:51 ` [PATCH v1 3/6] drm/panfrost: Unify panfrost_mmu_enable/disable common code Boris Brezillon
2025-03-12 13:24 ` Ariel D'Alessandro
2025-03-10 19:59 ` [PATCH v1 4/6] drm/panfrost: Add support for AARCH64_4K page table format Ariel D'Alessandro
2025-03-11 8:05 ` Boris Brezillon
2025-03-11 9:14 ` AngeloGioacchino Del Regno
2025-03-11 10:05 ` Boris Brezillon
2025-03-12 18:28 ` Ariel D'Alessandro
2025-03-12 17:49 ` Ariel D'Alessandro
2025-03-11 9:10 ` AngeloGioacchino Del Regno
2025-03-12 14:20 ` Ariel D'Alessandro
2025-03-12 14:49 ` AngeloGioacchino Del Regno
2025-03-10 19:59 ` [PATCH v1 5/6] drm/panfrost: Enable AARCH64_4K page table format on mediatek_mt8188 Ariel D'Alessandro
2025-03-11 8:06 ` Boris Brezillon
2025-03-13 19:04 ` Ariel D'Alessandro
2025-03-11 9:09 ` AngeloGioacchino Del Regno
2025-03-14 16:09 ` Ariel D'Alessandro
2025-03-10 19:59 ` [PATCH v1 6/6] drm/panfrost: Set HW_FEATURE_AARCH64_MMU feature flag on Bifrost models Ariel D'Alessandro
2025-03-11 8:08 ` Boris Brezillon
2025-03-14 16:25 ` Steven Price
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