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Mon, 17 Mar 2025 22:40:43 -0700 (PDT) Date: Tue, 18 Mar 2025 11:10:34 +0530 From: Manivannan Sadhasivam To: Ziyue Zhang Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, quic_qianyu@quicinc.com, quic_krichai@quicinc.com, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Konrad Dybcio Subject: Re: [PATCH v4 5/8] arm64: dts: qcom: qcs8300: enable pcie0 Message-ID: <20250318054034.j5stptttkoiutbk5@thinkpad> References: <20250310063103.3924525-1-quic_ziyuzhan@quicinc.com> <20250310063103.3924525-6-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250310063103.3924525-6-quic_ziyuzhan@quicinc.com> On Mon, Mar 10, 2025 at 02:31:00PM +0800, Ziyue Zhang wrote: > Add configurations in devicetree for PCIe0, including registers, clocks, > interrupts and phy setting sequence. > > Reviewed-by: Konrad Dybcio > Signed-off-by: Ziyue Zhang Reviewed-by: Manivannan Sadhasivam - Mani > --- > arch/arm64/boot/dts/qcom/qcs8300.dtsi | 168 +++++++++++++++++++++++++- > 1 file changed, 167 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > index 4a057f7c0d9f..5d05640c5e21 100644 > --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi > +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi > @@ -601,7 +601,7 @@ gcc: clock-controller@100000 { > #power-domain-cells = <1>; > clocks = <&rpmhcc RPMH_CXO_CLK>, > <&sleep_clk>, > - <0>, > + <&pcie0_phy>, > <0>, > <0>, > <0>, > @@ -711,6 +711,172 @@ mmss_noc: interconnect@17a0000 { > qcom,bcm-voters = <&apps_bcm_voter>; > }; > > + pcie0: pci@1c00000 { > + device_type = "pci"; > + compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; > + reg = <0x0 0x01c00000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf20>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x4000>, > + <0x0 0x40100000 0x0 0x100000>, > + <0x0 0x01c03000 0x0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, > + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; > + bus-range = <0x00 0xff>; > + > + dma-coherent; > + > + linux,pci-domain = <0>; > + num-lanes = <2>; > + > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + ; > + interrupt-names = "msi0", > + "msi1", > + "msi2", > + "msi3", > + "msi4", > + "msi5", > + "msi6", > + "msi7", > + "global"; > + > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a"; > + > + assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; > + assigned-clock-rates = <19200000>; > + > + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "pcie-mem", > + "cpu-pcie"; > + > + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, > + <0x100 &pcie_smmu 0x0001 0x1>; > + > + resets = <&gcc GCC_PCIE_0_BCR>, > + <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; > + reset-names = "pci", > + "link_down"; > + > + power-domains = <&gcc GCC_PCIE_0_GDSC>; > + > + phys = <&pcie0_phy>; > + phy-names = "pciephy"; > + > + status = "disabled"; > + > + pcie3_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + /* GEN 1 x1 */ > + opp-2500000 { > + opp-hz = /bits/ 64 <2500000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + opp-peak-kBps = <250000 1>; > + }; > + > + /* GEN 1 x2 and GEN 2 x1 */ > + opp-5000000 { > + opp-hz = /bits/ 64 <5000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + opp-peak-kBps = <500000 1>; > + }; > + > + /* GEN 2 x2 */ > + opp-10000000 { > + opp-hz = /bits/ 64 <10000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + opp-peak-kBps = <1000000 1>; > + }; > + > + /* GEN 3 x1 */ > + opp-8000000 { > + opp-hz = /bits/ 64 <8000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + opp-peak-kBps = <984500 1>; > + }; > + > + /* GEN 3 x2 and GEN 4 x1 */ > + opp-16000000 { > + opp-hz = /bits/ 64 <16000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <1969000 1>; > + }; > + > + /* GEN 4 x2 */ > + opp-32000000 { > + opp-hz = /bits/ 64 <32000000>; > + required-opps = <&rpmhpd_opp_nom>; > + opp-peak-kBps = <3938000 1>; > + }; > + }; > + }; > + > + pcie0_phy: phy@1c04000 { > + compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; > + reg = <0x0 0x01c04000 0x0 0x2000>; > + > + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_CLKREF_EN>, > + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, > + <&gcc GCC_PCIE_0_PIPE_CLK>, > + <&gcc GCC_PCIE_0_PIPEDIV2_CLK>, > + <&gcc GCC_PCIE_0_PHY_AUX_CLK>; > + clock-names = "cfg_ahb", > + "ref", > + "rchng", > + "pipe", > + "pipediv2", > + "phy_aux"; > + > + resets = <&gcc GCC_PCIE_0_PHY_BCR>; > + reset-names = "phy"; > + > + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; > + assigned-clock-rates = <100000000>; > + > + #clock-cells = <0>; > + clock-output-names = "pcie_0_pipe_clk"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > ufs_mem_hc: ufs@1d84000 { > compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > reg = <0x0 0x01d84000 0x0 0x3000>; > -- > 2.34.1 > -- மணிவண்ணன் சதாசிவம்