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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v3 00/29] x86: Leaf 0x2 and leaf 0x4 refactorings Date: Wed, 19 Mar 2025 13:21:08 +0100 Message-ID: <20250319122137.4004-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi, This is a v3 of the CPUID leaf 0x2 and leaf 0x4 code paths cleanup, in preparation for the x86-cpuid-db CPUID caching data model on top of this series. PQ is on top of tip/x86/cpu, as multiple patches from v1 and v2 got merged there (thanks a lot!). Changelog v3 ============ v2 CPUID headers refactoring, 02b63b33dfc9 ("x86/cpuid: Refactor ") got merged + more refactorings on top of it by Ingo. Apply review remarks from Boris: - Drop v2 "x86: treewide: Introduce x86_vendor_amd_or_hygon()" Apply review remarks from Ingo: - Divide the CPUID(2) changes further, quoting from review: "One does the functional change - this patch should be as small as possible. This patch turns a piece of 'Intel documents' property into 'actual code' that differs from the previous code, which may or may not regress in practice. The other does the factoring out and the introduction of ." This is now done as: patch 01/29 ("x86/cacheinfo: Use leaf 0x2 parsing helpers") patch 02/29 ("x86/cpu: Introduce and use leaf 0x2 parsing helpers") patch 03/29 ("x86/cacheinfo: Remove leaf 0x2 parsing loop") patch 04/29 ("x86/cpu: Remove leaf 0x2 parsing loop") Plus more testing and minor commit logs massaging overall. Changelog v2 ============ https://lkml.kernel.org/r/20250317164745.4754-1-darwi@linutronix.de Twelve patches got merged from v1, and they're now at tip/x86/core Apply Ingo Molnar's review remarks: - New header structure matching what is at : | +-- api.h +-- leaf_0x2_api.h `-- types.h - Standardize words usage and header file references across commit logs and comments (CPUID, vendor names, , etc.) - Use cpuid_ prefix for all new functions at and . - By the end of this series, leaf 0x2 call sites become: const struct leaf_0x2_table *entry; union leaf_0x2_regs regs; u8 *ptr; cpuid_get_leaf_0x2_regs(®s); for_each_leaf_0x2_entry(regs, ptr, entry) { switch (entry->c_type) { ... } } Changelog v1 ============ https://lkml.kernel.org/r/20250304085152.51092-1-darwi@linutronix.de As part of the onging x86-cpuid work [*], we've found that the handling of leaf 0x2 and leaf 0x4 code paths is difficult to work with in its current state. This was mostly due to the organic incremental growth of the x86/cpu and x86/cacheinfo logic since the very early Linux days. This series cleans up and refactors these code paths in preparation for the new x86-cpuid model. Summary: - Patches 1 to 3 are independent bugfixes that were discovered during this refactoring work. - Patches 4 to 10 are x86/cpu refactorings for code size and readability. - Patch 10 adds standardized and kernel-doc documented logic for accessing leaf 0x2 one byte descriptors. This makes the leaf 0x2 sanitization logic centralized in one place. x86/cpu and x86/cacheinfo is modified to use such macros afterwards. - Patches 11 to 28 refactors the x86/cacheinfo code. Beside readability, some of the unrelated logic (e.g. AMD northbridge cache_disable sysfs code) was first splitted from the generic leaf 0x4 code paths, at the structure relationships level, then gutted-out into their own files. - Patches 29 to 31 consolidate the existing (loop-based lookup) leaf 0x2 cache and TLB descriptor tables into one hash-based lookup table. This reduces code size while still keeping rodata size in check. Standardized macros for accessing this consolidated table are also added. Call sites can now just do: const struct leaf_0x2_table *entry; union leaf_0x2_regs regs; u8 *ptr; get_leaf_0x2_regs(®s); for_each_leaf_0x2_entry(regs, ptr, entry) { switch (entry->c_type) { ... } } without need to worry about sanitizing registers, skipping certain descriptors, etc. - Patches 32 and 33 uses the consolidated table above for x86/cpu and x86/cacheinfo. - Patches 34 to 40 provide the final set of x86/refactorings. This series is based on -rc5. It also applies cleanly on top of tip/x86/core. Note, testing was done by comparing below files: /proc/cpuinfo /sys/devices/system/cpu/ /sys/kernel/debug/x86/topo/ dmesg --notime | grep 'Last level [id]TLB entries' before and after on various old and new x86 machine configurations. [*] https://gitlab.com/x86-cpuid.org/x86-cpuid-db https://x86-cpuid.org 8<----- Ahmed S. Darwish (25): x86/cpu: Remove leaf 0x2 parsing loop x86/cacheinfo: Remove leaf 0x2 parsing loop x86/cpu: Introduce and use leaf 0x2 parsing helpers x86/cacheinfo: Use leaf 0x2 parsing helpers x86/cacheinfo: Constify _cpuid4_info_regs instances x86/cacheinfo: Align ci_info_init() assignment expressions x86/cacheinfo: Standardize _cpuid4_info_regs instance naming x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file x86/cacheinfo: Use sysfs_emit() for sysfs attributes show() x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors x86/cacheinfo: Use enums for cache descriptor types x86/cpu: Use enums for TLB descriptor types x86/cacheinfo: Use consolidated leaf 0x2 descriptor table x86/cpu: Use consolidated leaf 0x2 descriptor table x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic x86/cacheinfo: Separate Intel leaf 0x4 handling x86/cacheinfo: Extract out cache level topology ID calculation x86/cacheinfo: Extract out cache self-snoop checks x86/cacheinfo: Relocate leaf 0x4 cache_type mapping x86/cacheinfo: Introduce cpuid_amd_hygon_has_l3_cache() x86/cacheinfo: Apply maintainer-tip coding style fixes Thomas Gleixner (4): x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup x86/cacheinfo: Properly name amd_cpuid4()'s first parameter x86/cacheinfo: Use proper name for cacheinfo instances x86/cpu: Consolidate CPUID leaf 0x2 tables arch/x86/include/asm/cpuid.h | 1 + arch/x86/include/asm/cpuid/api.h | 9 + arch/x86/include/asm/cpuid/leaf_0x2_api.h | 96 ++ arch/x86/include/asm/cpuid/types.h | 92 ++ arch/x86/kernel/amd_nb.c | 7 +- arch/x86/kernel/cpu/Makefile | 5 +- arch/x86/kernel/cpu/amd_cache_disable.c | 301 ++++++ arch/x86/kernel/cpu/cacheinfo.c | 1042 +++++++-------------- arch/x86/kernel/cpu/cpu.h | 9 + arch/x86/kernel/cpu/cpuid_0x2_table.c | 128 +++ arch/x86/kernel/cpu/intel.c | 124 +-- 11 files changed, 980 insertions(+), 834 deletions(-) create mode 100644 arch/x86/include/asm/cpuid/leaf_0x2_api.h create mode 100644 arch/x86/kernel/cpu/amd_cache_disable.c create mode 100644 arch/x86/kernel/cpu/cpuid_0x2_table.c base-commit: 08d9bb5b0d89826fedc5204c8bd2463220465996 -- 2.48.1