From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from naesa04.arrow.com (naesa04.arrow.com [216.150.161.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE84E225413; Thu, 20 Mar 2025 10:55:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.150.161.24 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742468107; cv=none; b=dkAAKmUFzMzGZm9qyKBFoD8xszXX0NmP7nS6AynI+Os2xdKxab3qlvcZ8wp18kSUmN0G2T+/vOjYFkwybJ8MQwPZJFuvicZGajtUNMXucQpnK5+YdX2xH8KNmlPAqPALioNNu7Lfhc+lPNTrcYNUKeVc5fvynwk/NKWq4RTH14Y= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1742468107; c=relaxed/simple; bh=5heB6PuMYbbcCT5z+UhKDkhRC7FHz+vObUOuQmwwSh4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=AumkJin7HEraVvvguj2y9zXyYmEMkR7nSqBWyhEhUH8qYSSa9iXnDtvbSkYn+ygYw3sL0132TVme3mKOYEkhmO5Lvx5l+LquXyeJH8nxSXQg5phzWS7ENj3Mvsuq8qeRWDwMNnNXmc3IBKxum4OLq25gjkFMj93ywfp58K4RyfE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com; spf=pass smtp.mailfrom=einfochips.com; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b=DR7qanOk; arc=none smtp.client-ip=216.150.161.24 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=einfochips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=einfochips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=einfochips.com header.i=@einfochips.com header.b="DR7qanOk" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=einfochips.com; i=@einfochips.com; l=2333; q=dns/txt; s=NAESA-Selector1; t=1742468106; x=1774004106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5heB6PuMYbbcCT5z+UhKDkhRC7FHz+vObUOuQmwwSh4=; b=DR7qanOk22qQ3h7w9fJZROXzZsdYoVUcUg/JBN6XNXhCEVoIlwyU84xx 9tonTR/CsTftZ5qOV64Wkf7+cT4DkU0iuTEg5gdKqIF3Fxt2E+HhYtAa4 OlRfYqIiYCiu5tf5LFBqKt+VBsuKb6HI61ydtSoB+TowxOoIgt2yXT1LS 0Q2Le1sVHkY06Vy8ZSAlwTA17lMgAUw//p+mzdtzFGZ7urs6t7F45LU4F nd60jJwjv7N/gsK2ka8Rqh77saxlKj71cf5WdJyB58IDukOMVaqC3Of/M 6w5ty0eh9hd9xHRvA8ixThMJ1mi4apHUQ83y7qX7AuNtHJ7+jOLXLlznA w==; X-CSE-ConnectionGUID: q4OLy/sWSZiDnUSnbkcOdg== X-CSE-MsgGUID: /mvimzKzSxOV0mVRVi1JtQ== X-IronPort-AV: E=Sophos;i="6.14,261,1736838000"; d="scan'208";a="80263130" Received: from unknown (HELO eicahmirelay01.einfochips.com) ([10.100.49.50]) by naesa04out.arrow.com with ESMTP; 20 Mar 2025 04:55:04 -0600 Received: from AHMCPU1888.ap.corp.arrow.com ([172.25.5.100]) by eicahmirelay01.einfochips.com with Microsoft SMTPSVC(10.0.14393.4169); Thu, 20 Mar 2025 16:24:50 +0530 From: Pinkesh Vaghela To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner Cc: Paul Walmsley , Samuel Holland , Palmer Dabbelt , Albert Ou , Daniel Lezcano , Min Lin , Pinkesh Vaghela , Pritesh Patel , Yangyu Chen , Lad Prabhakar , Yu Chien Peter Lin , Charlie Jenkins , Kanak Shilledar , Darshan Prajapati , Neil Armstrong , Heiko Stuebner , Aradhya Bhatia , rafal@milecki.pl, Anup Patel , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree Date: Thu, 20 Mar 2025 16:24:49 +0530 Message-Id: <20250320105449.2094192-11-pinkesh.vaghela@einfochips.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> References: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 20 Mar 2025 10:54:50.0214 (UTC) FILETIME=[80BDA060:01DB9986] From: Min Lin Add initial board data for HiFive Premier P550 Development board Currently the data populated in this DT file describes the board DRAM configuration, UART and GPIO. Signed-off-by: Min Lin Co-developed-by: Pinkesh Vaghela Signed-off-by: Pinkesh Vaghela Reviewed-by: Samuel Holland Tested-by: Samuel Holland --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/eswin/Makefile | 2 ++ .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 +++++++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/eswin/Makefile create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index bff887d38abe..286a9939a8cb 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += allwinner subdir-y += canaan +subdir-y += eswin subdir-y += microchip subdir-y += renesas subdir-y += sifive diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile new file mode 100644 index 000000000000..224101ae471e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ESWIN) += eic7700-hifive-premier-p550.dtb diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts new file mode 100644 index 000000000000..131ed1fc6b2e --- /dev/null +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd. + */ + +/dts-v1/; + +#include "eic7700.dtsi" + +/ { + compatible = "sifive,hifive-premier-p550", "eswin,eic7700"; + model = "SiFive HiFive Premier P550"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; -- 2.25.1