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Fri, 21 Mar 2025 05:52:07 -0700 (PDT) Date: Fri, 21 Mar 2025 18:22:01 +0530 From: Manivannan Sadhasivam To: Sai Krishna Musham Cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, cassel@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, michal.simek@amd.com, bharat.kumar.gogada@amd.com, thippeswamy.havalige@amd.com Subject: Re: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for PCIe RP PERST# signal Message-ID: <20250321125201.2r6zcxwkivt7t6s3@thinkpad> References: <20250318092648.2298280-1-sai.krishna.musham@amd.com> <20250318092648.2298280-3-sai.krishna.musham@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250318092648.2298280-3-sai.krishna.musham@amd.com> On Tue, Mar 18, 2025 at 02:56:48PM +0530, Sai Krishna Musham wrote: > Add PCIe IP reset along with GPIO-based control for the PCIe Root > Port PERST# signal. Synchronizing the PCIe IP reset with the PERST# > signal's assertion and deassertion avoids Link Training failures. > > Add clear firewall after Link reset for CPM5NC. > > Adapt to use GPIO framework and make reset optional to maintain > backward compatibility with existing DTBs. > > Signed-off-by: Sai Krishna Musham > --- > Changes for v4: > - Add PCIe PERST# support for CPM5NC. > - Add PCIe IP reset along with PERST# to avoid Link Training Errors. > - Remove PCIE_T_PVPERL_MS define and PCIE_T_RRS_READY_MS after > PERST# deassert. > - Move PCIe PERST# assert and deassert logic to > xilinx_cpm_pcie_init_port() before cpm_pcie_link_up(), since > Interrupts enable and PCIe RP bridge enable should be done after > Link up. > - Update commit message. > > Changes for v3: > - Use PCIE_T_PVPERL_MS define. > > Changes for v2: > - Make the request GPIO optional. > - Correct the reset sequence as per PERST# > - Update commit message > --- > drivers/pci/controller/pcie-xilinx-cpm.c | 66 +++++++++++++++++++++++- > 1 file changed, 65 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c > index d0ab187d917f..fd1fee2f614b 100644 > --- a/drivers/pci/controller/pcie-xilinx-cpm.c > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c > @@ -6,6 +6,8 @@ > */ > > #include > +#include > +#include > #include > #include > #include > @@ -21,6 +23,13 @@ > #include "pcie-xilinx-common.h" > > /* Register definitions */ > +#define XILINX_CPM_PCIE0_RST 0x00000308 > +#define XILINX_CPM5_PCIE0_RST 0x00000318 > +#define XILINX_CPM5_PCIE1_RST 0x0000031C > +#define XILINX_CPM5NC_PCIE0_RST 0x00000324 > + > +#define XILINX_CPM5NC_PCIE0_FW 0x00001140 > + > #define XILINX_CPM_PCIE_REG_IDR 0x00000E10 > #define XILINX_CPM_PCIE_REG_IMR 0x00000E14 > #define XILINX_CPM_PCIE_REG_PSCR 0x00000E1C > @@ -99,6 +108,7 @@ struct xilinx_cpm_variant { > u32 ir_status; > u32 ir_enable; > u32 ir_misc_value; > + u32 cpm_pcie_rst; > }; > > /** > @@ -106,6 +116,8 @@ struct xilinx_cpm_variant { > * @dev: Device pointer > * @reg_base: Bridge Register Base > * @cpm_base: CPM System Level Control and Status Register(SLCR) Base > + * @crx_base: CPM Clock and Reset Control Registers Base > + * @cpm5nc_base: CPM5NC Control and Status Registers Base > * @intx_domain: Legacy IRQ domain pointer > * @cpm_domain: CPM IRQ domain pointer > * @cfg: Holds mappings of config space window > @@ -118,6 +130,8 @@ struct xilinx_cpm_pcie { > struct device *dev; > void __iomem *reg_base; > void __iomem *cpm_base; > + void __iomem *crx_base; > + void __iomem *cpm5nc_base; > struct irq_domain *intx_domain; > struct irq_domain *cpm_domain; > struct pci_config_window *cfg; > @@ -478,9 +492,42 @@ static int xilinx_cpm_setup_irq(struct xilinx_cpm_pcie *port) > static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port) > { > const struct xilinx_cpm_variant *variant = port->variant; > + struct device *dev = port->dev; > + struct gpio_desc *reset_gpio; > + > + /* Request the GPIO for PCIe reset signal */ > + reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); > + if (IS_ERR(reset_gpio)) { > + dev_err(dev, "Failed to request reset GPIO\n"); > + return; > + } > + > + /* Assert the reset signal */ > + gpiod_set_value(reset_gpio, 1); > > - if (variant->version == CPM5NC_HOST) > + /* Assert the PCIe IP reset */ > + writel_relaxed(0x1, port->crx_base + variant->cpm_pcie_rst); > + > + /* Controller specific delay */ > + udelay(50); > + > + /* Deassert the PCIe IP reset */ > + writel_relaxed(0x0, port->crx_base + variant->cpm_pcie_rst); > + > + /* Deassert the reset signal */ > + gpiod_set_value(reset_gpio, 0); > + mdelay(PCIE_T_RRS_READY_MS); > + > + if (variant->version == CPM5NC_HOST) { > + /* Clear Firewall */ On top of Krzk's review: What does this 'firewall' mean? Clearly, not something defined in the PCIe spec. Also, you made it independent of PERST# line. So is it really needed for platforms not supporting PERST#? - Mani -- மணிவண்ணன் சதாசிவம்