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[130.180.211.218]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d830f5b41sm75979335e9.27.2025.03.28.08.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Mar 2025 08:15:51 -0700 (PDT) From: Daniel Lezcano To: wim@linux-watchdog.org Cc: linux@roeck-us.net, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org, daniel.lezcano@linaro.org, S32@nxp.com, Ghennadi Procopciuc , Thomas Fossati , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 1/2] dt-bindings: watchdog: Add NXP Software Watchdog Timer Date: Fri, 28 Mar 2025 16:15:13 +0100 Message-ID: <20250328151516.2219971-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe the Software Watchdog Timer available on the S32G platforms. Cc: Ghennadi Procopciuc Cc: Thomas Fossati Signed-off-by: Daniel Lezcano --- .../bindings/watchdog/nxp,s32g-wdt.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) create mode 100644 Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml diff --git a/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml new file mode 100644 index 000000000000..06ead743d5c1 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nxp,s32g-wdt.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/nxp,s32g-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP Software Watchdog Timer + +maintainers: + - Daniel Lezcano + +description: + The System Timer Module supports commonly required system and + application software timing functions. STM includes a 32-bit + count-up timer and four 32-bit compare channels with a separate + interrupt source for each channel. The timer is driven by the STM + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + enum: + - nxp,s32g-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + watchdog@0x40100000 { + compatible = "nxp,s32g-wdt"; + reg = <0x40100000 0x1000>; + clocks = <&clks 0x3a>; + timeout-sec = <10>; + }; -- 2.43.0